blob: b758e94e793178847011cf1c99fec0443fc6f0a1 [file] [log] [blame]
wdenk4a551702003-10-08 23:26:14 +00001/*
2 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
wdenkc935d3b2004-01-03 19:43:48 +00004 * Stephan Linz <linz@li-pro.net>
wdenk4a551702003-10-08 23:26:14 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
wdenkec4c5442004-02-09 23:12:24 +000028/***********************************************************************
29 * Include the whole NIOS CPU configuration.
wdenkc935d3b2004-01-03 19:43:48 +000030 *
wdenkec4c5442004-02-09 23:12:24 +000031 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
wdenkc935d3b2004-01-03 19:43:48 +000032 *
wdenkec4c5442004-02-09 23:12:24 +000033 ***********************************************************************/
wdenkc935d3b2004-01-03 19:43:48 +000034
35#if defined(CONFIG_NIOS_SAFE_32)
wdenkec4c5442004-02-09 23:12:24 +000036#include <configs/DK1C20_safe_32.h>
wdenkc935d3b2004-01-03 19:43:48 +000037#elif defined(CONFIG_NIOS_STANDARD_32)
wdenkec4c5442004-02-09 23:12:24 +000038#include <configs/DK1C20_standard_32.h>
wdenkc935d3b2004-01-03 19:43:48 +000039#else
40#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
41#endif
42
wdenk4a551702003-10-08 23:26:14 +000043/*------------------------------------------------------------------------
44 * BOARD/CPU -- TOP-LEVEL
45 *----------------------------------------------------------------------*/
46#define CONFIG_NIOS 1 /* NIOS-32 core */
47#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
wdenkc935d3b2004-01-03 19:43:48 +000048#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
49#define CFG_HZ 1000 /* 1 msec time tick */
50#undef CFG_CLKS_IN_HZ
wdenkc837dcb2004-01-20 23:12:12 +000051#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
wdenk4a551702003-10-08 23:26:14 +000052
53/*------------------------------------------------------------------------
wdenkc935d3b2004-01-03 19:43:48 +000054 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
wdenk4a551702003-10-08 23:26:14 +000055 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +000056#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
57
58#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
59#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
60
61#else
62#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
63#endif
64
65#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
66#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
67#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
wdenk4a551702003-10-08 23:26:14 +000068
69/*------------------------------------------------------------------------
70 * MEMORY ORGANIZATION - For the most part, you can put things pretty
71 * much anywhere. This is pretty flexible for Nios. So here we make some
72 * arbitrary choices & assume that the monitor is placed at the end of
73 * a memory resource (so you must make sure TEXT_BASE is chosen
74 * appropriately).
75 *
76 * -The heap is placed below the monitor.
77 * -Global data is placed below the heap.
78 * -The stack is placed below global data (&grows down).
79 *----------------------------------------------------------------------*/
80#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
wdenk4a551702003-10-08 23:26:14 +000081#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
82#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
83
84#define CFG_MONITOR_BASE TEXT_BASE
85#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
wdenkc935d3b2004-01-03 19:43:48 +000086#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
wdenk4a551702003-10-08 23:26:14 +000087#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
88
89/*------------------------------------------------------------------------
wdenkc935d3b2004-01-03 19:43:48 +000090 * FLASH (AM29LV065D)
wdenk4a551702003-10-08 23:26:14 +000091 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +000092#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
93
94#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
95#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
wdenk4a551702003-10-08 23:26:14 +000096#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
97#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
98#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
99#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
wdenkc935d3b2004-01-03 19:43:48 +0000100#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
101
102#else
103#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
104#endif
wdenk4a551702003-10-08 23:26:14 +0000105
106/*------------------------------------------------------------------------
107 * ENVIRONMENT
108 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +0000109#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
110
wdenk4a551702003-10-08 23:26:14 +0000111#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
wdenkc935d3b2004-01-03 19:43:48 +0000112#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
113#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
wdenk4a551702003-10-08 23:26:14 +0000114#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
115
wdenkc935d3b2004-01-03 19:43:48 +0000116#else
117#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
118#endif
119
wdenk4a551702003-10-08 23:26:14 +0000120/*------------------------------------------------------------------------
121 * CONSOLE
122 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +0000123#if (CFG_NIOS_CPU_UART_NUMS != 0)
124
125#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
126
127#if (CFG_NIOS_CPU_UART0_BR != 0)
128#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
129#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
130#else
131#undef CFG_NIOS_FIXEDBAUD
wdenk4a551702003-10-08 23:26:14 +0000132#define CONFIG_BAUDRATE 115200
wdenkc935d3b2004-01-03 19:43:48 +0000133#endif
134
135#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
136
137#else
138#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
139#endif
wdenk4a551702003-10-08 23:26:14 +0000140
141/*------------------------------------------------------------------------
142 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
143 * so an avalon bus timer is required.
144 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +0000145#if (CFG_NIOS_CPU_TIMER_NUMS != 0)
146
147#if (CFG_NIOS_CPU_TICK_TIMER == 0)
148
wdenk63e73c92004-02-23 22:22:28 +0000149#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
150#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
151
152#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
153
154#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
155#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
156#else
157#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
158#endif
159
160#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
161
162#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
163
164#if (CFG_HZ <= 1000)
165#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
166#else
167#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
168#endif
169
170#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
171
172#else
173#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
174#endif
wdenkc935d3b2004-01-03 19:43:48 +0000175
176#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
177
178#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
179#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
180
wdenk63e73c92004-02-23 22:22:28 +0000181#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
182
wdenkc935d3b2004-01-03 19:43:48 +0000183#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
184#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
185#else
wdenk63e73c92004-02-23 22:22:28 +0000186#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
187#endif
188
189#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
190
191#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
192
193#if (CFG_HZ <= 1000)
194#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
195#else
196#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
197#endif
198
199#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
200
201#else
202#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
wdenkc935d3b2004-01-03 19:43:48 +0000203#endif
204
205#endif /* CFG_NIOS_CPU_TICK_TIMER */
206
207#else
208#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
209#endif
wdenk4a551702003-10-08 23:26:14 +0000210
211/*------------------------------------------------------------------------
wdenk180d3f72004-01-04 16:28:35 +0000212 * Ethernet
wdenk4a551702003-10-08 23:26:14 +0000213 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +0000214#if (CFG_NIOS_CPU_LAN_NUMS == 1)
215
216#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
217
wdenkc935d3b2004-01-03 19:43:48 +0000218#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
219#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
220#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
221
222#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
223#define CONFIG_SMC_USE_32_BIT 1
224#else /* no */
225#undef CONFIG_SMC_USE_32_BIT
226#endif
227
228#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
229
230 /********************************************/
231 /* !!! CS8900 is __not__ tested on NIOS !!! */
232 /********************************************/
233#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
234#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
235
236#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
237#undef CS8900_BUS16
238#define CS8900_BUS32 1
239#else /* no */
240#define CS8900_BUS16 1
241#undef CS8900_BUS32
242#endif
243
244#else
245#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
246#endif
wdenk4a551702003-10-08 23:26:14 +0000247
248#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
249#define CONFIG_NETMASK 255.255.255.0
250#define CONFIG_IPADDR 192.168.2.21
251#define CONFIG_SERVERIP 192.168.2.16
252
wdenkc935d3b2004-01-03 19:43:48 +0000253#else
254#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
255#endif
256
257/*------------------------------------------------------------------------
258 * STATUS LEDs
259 *----------------------------------------------------------------------*/
260#if (CFG_NIOS_CPU_PIO_NUMS != 0)
261
262#if (CFG_NIOS_CPU_LED_PIO == 0)
263
264#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
265
266#elif (CFG_NIOS_CPU_LED_PIO == 1)
267
268#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
269
270#elif (CFG_NIOS_CPU_LED_PIO == 2)
271
272#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
273#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
274#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
275
276#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
277#define STATUS_LED_WRONLY 1
278#else
279#undef STATUS_LED_WRONLY
280#endif
281
282#elif (CFG_NIOS_CPU_LED_PIO == 3)
283
284#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
285
286#elif (CFG_NIOS_CPU_LED_PIO == 4)
287
288#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
289
290#elif (CFG_NIOS_CPU_LED_PIO == 5)
291
292#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
293
294#elif (CFG_NIOS_CPU_LED_PIO == 6)
295
296#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
297
298#elif (CFG_NIOS_CPU_LED_PIO == 7)
299
300#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
301
302#elif (CFG_NIOS_CPU_LED_PIO == 8)
303
304#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
305
306#elif (CFG_NIOS_CPU_LED_PIO == 9)
307
308#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
309
310#else
311#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
312#endif
313
314#define CONFIG_STATUS_LED 1 /* enable status led driver */
315
316#define STATUS_LED_BIT (1 << 0) /* LED[0] */
317#define STATUS_LED_STATE STATUS_LED_BLINKING
318#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
319#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
320#define STATUS_LED_BOOT 0 /* boot LED */
321
322#if (STATUS_LED_BITS > 1)
323#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
324#define STATUS_LED_STATE1 STATUS_LED_OFF
325#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
326#define STATUS_LED_RED 1 /* fail LED */
327#endif
328
329#if (STATUS_LED_BITS > 2)
330#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
331#define STATUS_LED_STATE2 STATUS_LED_OFF
332#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
333#define STATUS_LED_YELLOW 2 /* info LED */
334#endif
335
336#if (STATUS_LED_BITS > 3)
337#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
338#define STATUS_LED_STATE3 STATUS_LED_OFF
339#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
340#define STATUS_LED_GREEN 3 /* info LED */
341#endif
342
343#define STATUS_LED_PAR 1 /* makes status_led.h happy */
344
345#endif /* CFG_NIOS_CPU_PIO_NUMS */
346
347/*------------------------------------------------------------------------
348 * SEVEN SEGMENT LED DISPLAY
349 *----------------------------------------------------------------------*/
350#if (CFG_NIOS_CPU_PIO_NUMS != 0)
351
352#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
353
wdenkec4c5442004-02-09 23:12:24 +0000354#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000355
356#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
357
wdenkec4c5442004-02-09 23:12:24 +0000358#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000359
360#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
361
wdenkec4c5442004-02-09 23:12:24 +0000362#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000363
364#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
365
366#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
367#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
368#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
369
370#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
371#define SEVENSEG_WRONLY 1
372#else
373#undef SEVENSEG_WRONLY
374#endif
375
376#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
377
wdenkec4c5442004-02-09 23:12:24 +0000378#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000379
380#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
381
wdenkec4c5442004-02-09 23:12:24 +0000382#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000383
384#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
385
wdenkec4c5442004-02-09 23:12:24 +0000386#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000387
388#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
389
wdenkec4c5442004-02-09 23:12:24 +0000390#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000391
392#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
393
wdenkec4c5442004-02-09 23:12:24 +0000394#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000395
396#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
397
wdenkec4c5442004-02-09 23:12:24 +0000398#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
wdenkc935d3b2004-01-03 19:43:48 +0000399
400#else
401#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
402#endif
403
404#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
405
406/*
407 * Dual 7-Segment Display pin assignment -- read more in your
408 * "Nios Development Board Reference Manual"
409 *
410 *
411 * (U8) HI:D[15..8] (U9) LO:D[7..0]
412 * ______ ______
413 * | D14 | | D6 |
414 * | | | |
415 * D9| |D13 D1| |D5
416 * |______| |______| ___
417 * | D8 | | D0 | | A |
418 * | | | | F|___|B
419 * D10| |D12 D2| |D4 | G |
420 * |______| |______| E|___|C
421 * D11 * D3 * D *
422 * D15 D7 DP
423 *
424 */
425#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
426#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
427#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
428#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
429#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
430#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
431#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
432#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
433#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
434
435#endif /* CFG_NIOS_CPU_PIO_NUMS */
436
wdenk4a551702003-10-08 23:26:14 +0000437/*------------------------------------------------------------------------
wdenk180d3f72004-01-04 16:28:35 +0000438 * ASMI - Active Serial Memory Interface.
439 *
440 * ASMI is for Cyclone devices only and only works when the configuration
441 * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
442 *----------------------------------------------------------------------*/
wdenk5653fc32004-02-08 22:55:38 +0000443#define CONFIG_NIOS_ASMI /* Enable ASMI */
444#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
wdenk180d3f72004-01-04 16:28:35 +0000445
446/*------------------------------------------------------------------------
wdenk4a551702003-10-08 23:26:14 +0000447 * COMMANDS
448 *----------------------------------------------------------------------*/
449#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
450 CFG_CMD_ASKENV | \
451 CFG_CMD_BEDBUG | \
452 CFG_CMD_BMP | \
453 CFG_CMD_BSP | \
454 CFG_CMD_CACHE | \
455 CFG_CMD_DATE | \
456 CFG_CMD_DOC | \
457 CFG_CMD_DTT | \
458 CFG_CMD_EEPROM | \
459 CFG_CMD_ELF | \
460 CFG_CMD_FAT | \
461 CFG_CMD_FDC | \
462 CFG_CMD_FDOS | \
463 CFG_CMD_HWFLOW | \
464 CFG_CMD_IDE | \
465 CFG_CMD_I2C | \
466 CFG_CMD_JFFS2 | \
467 CFG_CMD_KGDB | \
468 CFG_CMD_NAND | \
wdenke7c85682004-02-27 08:21:54 +0000469 CFG_CMD_NFS | \
wdenk4a551702003-10-08 23:26:14 +0000470 CFG_CMD_MMC | \
471 CFG_CMD_MII | \
472 CFG_CMD_PCI | \
473 CFG_CMD_PCMCIA | \
wdenke4cc71a2004-05-19 21:33:14 +0000474 CFG_CMD_REISER | \
wdenk4a551702003-10-08 23:26:14 +0000475 CFG_CMD_SCSI | \
476 CFG_CMD_SPI | \
477 CFG_CMD_VFD | \
wdenk48abe7b2004-06-09 10:15:00 +0000478 CFG_CMD_USB | \
479 CFG_CMD_XIMG ) )
wdenk4a551702003-10-08 23:26:14 +0000480
481
482#include <cmd_confdefs.h>
483
484/*------------------------------------------------------------------------
485 * KGDB
486 *----------------------------------------------------------------------*/
487#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
488#define CONFIG_KGDB_BAUDRATE 9600
489#endif
490
491/*------------------------------------------------------------------------
492 * MISC
493 *----------------------------------------------------------------------*/
wdenkc935d3b2004-01-03 19:43:48 +0000494#define CFG_LONGHELP /* undef to save memory */
495#define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */
496#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk4a551702003-10-08 23:26:14 +0000497#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkc935d3b2004-01-03 19:43:48 +0000498#define CFG_MAXARGS 16 /* max number of command args*/
499#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
wdenk4a551702003-10-08 23:26:14 +0000500
wdenkc935d3b2004-01-03 19:43:48 +0000501#if (CFG_SRAM_SIZE != 0)
502#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
503#else
504#undef CFG_LOAD_ADDR
505#endif
506
507#if (CFG_SDRAM_SIZE != 0)
508#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
509#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
510#else
511#undef CFG_MEMTEST_START
512#undef CFG_MEMTEST_END
513#endif
wdenk4a551702003-10-08 23:26:14 +0000514
515
516#endif /* __CONFIG_H */