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wdenkba91e262005-05-30 23:55:42 +00001/*
2 * (C) Copyright 2004
3 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
4 *
5 * Support for the Elmeg VoVPN Gateway Module
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/* define cpu used */
27#define CONFIG_MPC8272 1
28
29/* define busmode: 8260 */
30#undef CONFIG_BUSMODE_60x
31
32/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
33#ifdef CONFIG_CLKIN_66MHz
34#define CONFIG_8260_CLKIN 66666666 /* in Hz */
35#else
36#define CONFIG_8260_CLKIN 100000000 /* in Hz */
37#endif
38
39/* call board_early_init_f */
40#define CONFIG_BOARD_EARLY_INIT_F 1
41
42/* have misc_init_r() function */
43#define CONFIG_MISC_INIT_R 1
44
45/* have reset_phy_r() function */
46#define CONFIG_RESET_PHY_R 1
47
48/* have special reset function */
49#define CONFIG_HAVE_OWN_RESET 1
50
51/* allow serial and ethaddr to be overwritten */
52#define CONFIG_ENV_OVERWRITE
53
54/* watchdog disabled */
55#undef CONFIG_WATCHDOG
56
57/* include support for bzip2 compressed images */
58#undef CONFIG_BZIP2
59
60/* status led */
61#undef CONFIG_STATUS_LED /* XXX jse */
62
63/* vendor parameter protection */
64#define CONFIG_ENV_OVERWRITE
65
66/*
67 * select serial console configuration
68 *
69 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
70 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
71 * for SCC).
72 */
73#define CONFIG_CONS_ON_SMC
74#undef CONFIG_CONS_ON_SCC
75#undef CONFIG_CONS_NONE
76#define CONFIG_CONS_INDEX 1
77
78/* serial port default baudrate */
79#define CONFIG_BAUDRATE 115200
80
81/* echo on for serial download */
82#define CONFIG_LOADS_ECHO 1
83
84/* don't allow baudrate change */
85#undef CFG_LOADS_BAUD_CHANGE
86
87/* supported baudrates */
88#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89
90/*
91 * select ethernet configuration
92 *
93 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
94 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
95 * for FCC)
96 *
97 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
98 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
99 * from CONFIG_COMMANDS to remove support for networking.
100 */
101#undef CONFIG_ETHER_ON_SCC
102#define CONFIG_ETHER_ON_FCC
103#undef CONFIG_ETHER_NONE
104
105#ifdef CONFIG_ETHER_ON_FCC
106
107/* which SCC/FCC channel for ethernet */
108#define CONFIG_ETHER_INDEX 1
109
110/* Marvell Switch SMI base addr */
111#define CFG_PHY_ADDR 0x10
112
113/* FCC1 RMII REFCLK is CLK10 */
114#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
115#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
116
117/* BDs and buffers on 60x bus */
118#define CFG_CPMFCR_RAMTYPE 0
119
120/* Local Protect, Full duplex, Flowcontrol, RMII */
121#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
122 FCC_PSMR_FCE|FCC_PSMR_RMII)
123
124/* bit-bang MII PHY management */
125#define CONFIG_BITBANGMII
126
127#define MDIO_PORT 1 /* Port B */
128#define CFG_MDIO_PIN 0x00002000 /* PB18 */
129#define CFG_MDC_PIN 0x00001000 /* PB19 */
130#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
131#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
132#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
133#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
134 else iop->pdat &= ~CFG_MDIO_PIN
135#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
136 else iop->pdat &= ~CFG_MDC_PIN
137#define MIIDELAY udelay(1)
138
139#endif
140
141/* configure commands */
142#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \
143 CFG_CMD_BDI | \
144 CFG_CMD_CONSOLE | \
145 CFG_CMD_ECHO | \
146 CFG_CMD_ENV | \
147 CFG_CMD_FLASH | \
148 CFG_CMD_IMI | \
149 CFG_CMD_IMLS | \
150 CFG_CMD_LOADB | \
151 CFG_CMD_MEMORY | \
152 CFG_CMD_MISC | \
153 CFG_CMD_NET | \
154 CFG_CMD_PING | \
155 CFG_CMD_RUN )
156
157/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
158#include <cmd_confdefs.h>
159
160/*
161 * boot options & environment
162 */
163#define CONFIG_BOOTDELAY 3
164#define CONFIG_BOOTCOMMAND "run flash_self"
165#undef CONFIG_BOOTARGS
166#define CONFIG_EXTRA_ENV_SETTINGS \
167"clean_nv=erase fff20000 ffffffff\0" \
168"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 $(filesize); tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 $(filesize)\0" \
169"update_lx=tftp 100000 $(kernel); erase $(kernel_addr) ffefffff; cp.b 100000 $(kernel_addr) $(filesize)\0" \
170"update_fs=tftp 100000 $(fs).$(fstype); erase ff840000 ffdfffff; cp.b 100000 ff840000 $(filesize)\0" \
171"update_ub=tftp 100000 $(uboot); protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 $(filesize); protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
172"flashargs=setenv bootargs root=$(rootdev) rw rootfstype=$(fstype)\0" \
173"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
174"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
175"addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) panic=1\0" \
176"net_nfs=tftpboot 400000 $(kernel); run nfsargs addip addmisc; bootm\0" \
177"net_self=tftpboot 400000 $(kernel); run flashargs addmisc; bootm\0" \
178"flash_self=run flashargs addmisc; bootm $(kernel_addr)\0" \
179"flash_nfs=run nfsargs addip addmisc; bootm $(kernel_addr)\0" \
180"fstype=cramfs\0" \
181"rootpath=/root_fs\0" \
182"uboot=PPC/u-boot.bin\0" \
183"kernel=PPC/uImage\0" \
184"kernel_addr=ffe00000\0" \
185"fs=PPC/root_fs\0" \
186"console=ttyS0\0" \
187"netdev=eth0\0" \
188"rootdev=31:3\0" \
189"ethaddr=00:09:4f:01:02:03\0" \
190"ipaddr=10.0.0.201\0" \
191"netmask=255.255.255.0\0" \
192"serverip=10.0.0.136\0" \
193"gatewayip=10.0.0.10\0" \
194"hostname=bastard\0" \
195""
196
197
198/*
199 * miscellaneous configurable options
200 */
201
202/* undef to save memory */
203#define CFG_LONGHELP
204
205/* monitor command prompt */
206#define CFG_PROMPT "=> "
207
208/* console i/o buffer size */
209#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
210#define CFG_CBSIZE 1024
211#else
212#define CFG_CBSIZE 256
213#endif
214
215/* print buffer size */
216#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
217
218/* max number of command args */
219#define CFG_MAXARGS 16
220
221/* boot argument buffer size */
222#define CFG_BARGSIZE CFG_CBSIZE
223
224/* memtest works on */
225#define CFG_MEMTEST_START 0x00100000
226/* 1 ... 15 MB in DRAM */
227#define CFG_MEMTEST_END 0x00f00000
228/* full featured memtest */
229#define CFG_ALT_MEMTEST
230
231/* default load address */
232#define CFG_LOAD_ADDR 0x00100000
233
234/* decrementer freq: 1 ms ticks */
235#define CFG_HZ 1000
236
237/* configure flash */
238#define CFG_FLASH_BASE 0xff800000
239#define CFG_MAX_FLASH_BANKS 1
240#define CFG_MAX_FLASH_SECT 64
241#define CFG_FLASH_SIZE 8
242#undef CFG_FLASH_16BIT
243#define CFG_FLASH_ERASE_TOUT 240000
244#define CFG_FLASH_WRITE_TOUT 500
245#define CFG_FLASH_LOCK_TOUT 500
246#define CFG_FLASH_UNLOCK_TOUT 10000
247#define CFG_FLASH_PROTECTION
248
249/* monitor in flash */
250#define CFG_MONITOR_OFFSET 0x00700000
251
252/* environment in flash */
253#define CFG_ENV_IS_IN_FLASH 1
254#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000)
255#define CFG_ENV_SIZE 0x00020000
256#define CFG_ENV_SECT_SIZE 0x00020000
257
258/*
259 * Initial memory map for linux
260 * For booting Linux, the board info and command line data
261 * have to be in the first 8 MB of memory, since this is
262 * the maximum mapped by the Linux kernel during initialization.
263 */
wdenka87589d2005-06-10 10:00:19 +0000264#define CFG_BOOTMAPSZ (8 << 20)
wdenkba91e262005-05-30 23:55:42 +0000265
266/* hard reset configuration words */
267#ifdef CONFIG_CLKIN_66MHz
268#define CFG_HRCW_MASTER 0x04643050
269#else
270#error NO HRCW FOR 100MHZ SPECIFIED !!!
271#endif
272#define CFG_HRCW_SLAVE1 0x00000000
273#define CFG_HRCW_SLAVE2 0x00000000
274#define CFG_HRCW_SLAVE3 0x00000000
275#define CFG_HRCW_SLAVE4 0x00000000
276#define CFG_HRCW_SLAVE5 0x00000000
277#define CFG_HRCW_SLAVE6 0x00000000
278#define CFG_HRCW_SLAVE7 0x00000000
279
280/* internal memory mapped register */
281#define CFG_IMMR 0xF0000000
282
283/* definitions for initial stack pointer and data area (in DPRAM) */
284#define CFG_INIT_RAM_ADDR CFG_IMMR
285#define CFG_INIT_RAM_END 0x2000
286#define CFG_GBL_DATA_SIZE 128
287#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
288#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
289
290/*
291 * Start addresses for the final memory configuration
292 * (Set up by the startup code)
293 * Please note that CFG_SDRAM_BASE _must_ start at 0
294 */
295#define CFG_SDRAM_BASE 0x00000000
296#define CFG_SDRAM_SIZE (32*1024*1024)
297#define CFG_MONITOR_BASE TEXT_BASE
298#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
299#define CFG_MONITOR_LEN 0x00020000
300#define CFG_MALLOC_LEN 0x00020000
301
302/* boot flags */
303#define BOOTFLAG_COLD 0x01 /* normal power-on */
304#define BOOTFLAG_WARM 0x02 /* software reboot */
305
306/* cache configuration */
307#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */
308#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
309#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */
310#endif
311
312/*
313 * HIDx - Hardware Implementation-dependent Registers
314 *-----------------------------------------------------------------------
315 * HID0 also contains cache control - initially enable both caches and
316 * invalidate contents, then the final state leaves only the instruction
317 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
318 * but Soft reset does not.
319 *
320 * HID1 has only read-only information - nothing to set.
321 */
322#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\
323 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
324#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
325#define CFG_HID2 0
326
327/* RMR - reset mode register - turn on checkstop reset enable */
328#define CFG_RMR RMR_CSRE
329
330/* BCR - bus configuration */
331#define CFG_BCR 0x00000000
332
333/* SIUMCR - siu module configuration */
334#define CFG_SIUMCR 0x4905c000
335
336/* SYPCR - system protection control */
337#if defined(CONFIG_WATCHDOG)
338#define CFG_SYPCR 0xffffff87
339#else
340#define CFG_SYPCR 0xffffff83
341#endif
342
343/* TMCNTSC - time counter status and control */
344/* clear interrupts XXX jse */
wdenka87589d2005-06-10 10:00:19 +0000345/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
wdenkba91e262005-05-30 23:55:42 +0000346#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
347 TMCNTSC_TCF|TMCNTSC_TCE)
348
349/* PISCR - periodic interrupt status and control */
350/* clear interrupts XXX jse */
wdenka87589d2005-06-10 10:00:19 +0000351/*#define CFG_PISCR (PISCR_PS) */
wdenkba91e262005-05-30 23:55:42 +0000352#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
353
354/* SCCR - system clock control */
355#define CFG_SCCR 0x000001a9
356
357/* RCCR - risc controller configuration */
358#define CFG_RCCR 0
359
360/*
361 * MEMORY MAP
362 * ----------
363 * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
364 * CS1 - SDRAM 32MB/64Bit base=0x00000000
365 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
366 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
367 * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
368 * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
369 * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
370 * x - IMMR 384KB base=0xf0000000
371 */
372/* XXX jse 100MHz TODO */
373#define CFG_BR0_PRELIM 0xff800801
374#define CFG_OR0_PRELIM 0xff801e44
375#define CFG_BR1_PRELIM 0x00000041
376#define CFG_OR1_PRELIM 0xfe002ec0
377#if 1
378#define CFG_BR2_PRELIM 0xf0101001
379#define CFG_OR2_PRELIM 0xfff00ef4
380#define CFG_BR3_PRELIM 0xf0201001
381#define CFG_OR3_PRELIM 0xfff00ef4
382#define CFG_BR4_PRELIM 0xf0301001
383#define CFG_OR4_PRELIM 0xfff00ef4
384#define CFG_BR5_PRELIM 0xf0401001
385#define CFG_OR5_PRELIM 0xfff00ef4
386#else
387#define CFG_BR2_PRELIM 0xf0101081
388#define CFG_OR2_PRELIM 0xfff00104
389#define CFG_BR3_PRELIM 0xf0201081
390#define CFG_OR3_PRELIM 0xfff00104
391#define CFG_BR4_PRELIM 0xf0301081
392#define CFG_OR4_PRELIM 0xfff00104
393#define CFG_BR5_PRELIM 0xf0401081
394#define CFG_OR5_PRELIM 0xfff00104
395#endif
396#define CFG_BR7_PRELIM 0xf0500881
397#define CFG_OR7_PRELIM 0xffff8104
398#define CFG_MPTPR 0x2700
399#define CFG_PSDMR 0x822a2452 /* optimal */
wdenka87589d2005-06-10 10:00:19 +0000400/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */
wdenkba91e262005-05-30 23:55:42 +0000401#define CFG_PSRT 0x1a
402
403/* "bad" address */
404#define CFG_RESET_ADDRESS 0x40000000
405
406#endif /* __CONFIG_H */