Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b2101df305212dd3b98486cbec1d1f15da0832de / . / include / configs / hsdk.h
blob: 2177fafcdc0656a452213956956d3851432519e9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]2/*
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]4 */
5
6#ifndef _CONFIG_HSDK_H_
7#define _CONFIG_HSDK_H_
8
9#include <linux/sizes.h>
10
11/*
12 * CPU configuration
13 */
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300[diff] [blame]14#define NR_CPUS 4
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]15#define ARC_PERIPHERAL_BASE 0xF0000000
16#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
18
19/*
20 * Memory configuration
21 */
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]22
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]23#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
24#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
Tom Riniaa6e94d2022-11-16 13:10:37 -0500[diff] [blame]25#define CFG_SYS_SDRAM_SIZE SZ_1G
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]26
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]27/*
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]28 * UART configuration
29 */
Tom Rini91092132022-11-16 13:10:28 -0500[diff] [blame]30#define CFG_SYS_NS16550_CLK 33330000
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]31
32/*
33 * Ethernet PHY configuration
34 */
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]35
36/*
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]37 * Environment settings
38 */
Tom Rini0613c362022-12-04 10:03:50 -0500[diff] [blame]39#define CFG_EXTRA_ENV_SETTINGS \
Eugeniy Paltsev9ddcfef2018-06-04 14:52:32 +0300[diff] [blame]40 "upgrade=if mmc rescan && " \
41 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
42 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
43 "\"Fail to upgrade.\n" \
44 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
45 "; fi\0" \
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300[diff] [blame]46 "core_dccm_0=0x10\0" \
47 "core_dccm_1=0x6\0" \
48 "core_dccm_2=0x10\0" \
49 "core_dccm_3=0x6\0" \
50 "core_iccm_0=0x10\0" \
51 "core_iccm_1=0x6\0" \
52 "core_iccm_2=0x10\0" \
53 "core_iccm_3=0x6\0" \
54 "core_mask=0xF\0" \
55 "dcache_ena=0x1\0" \
56 "icache_ena=0x1\0" \
57 "non_volatile_limit=0xE\0" \
58 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
59setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
60setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
61 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
62setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
63setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
64 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
65setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
66setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
67 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
68setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
69setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
70 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
71setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
72setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
73 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
74setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
75setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
76setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
77 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
78setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
79setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
80setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
81setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
82 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
83setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
84setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
85setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
86setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
87setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
88
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300[diff] [blame]89/* Cli configuration */
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300[diff] [blame]90
91/*
92 * Callback configuration
93 */
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300[diff] [blame]94
Alexey Brodkin67482f52016-11-25 16:23:43 +0300[diff] [blame]95#endif /* _CONFIG_HSDK_H_ */