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Tor Krill9536dfc2008-03-15 15:40:26 +01001/*
2 * (C) Copyright 2008
3 * Tor Krill, Excito Elektronik i Skåne , tor@excito.com
4 *
5 * Modelled after the ds1337 driver
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tor Krill9536dfc2008-03-15 15:40:26 +01008 */
9
10/*
11 * Date & Time support (no alarms) for Intersil
12 * ISL1208 Real Time Clock (RTC).
13 */
14
15#include <common.h>
16#include <command.h>
17#include <rtc.h>
18#include <i2c.h>
19
20/*---------------------------------------------------------------------*/
21#ifdef DEBUG_RTC
22#define DEBUGR(fmt,args...) printf(fmt ,##args)
23#else
24#define DEBUGR(fmt,args...)
25#endif
26/*---------------------------------------------------------------------*/
27
28/*
29 * RTC register addresses
30 */
31
32#define RTC_SEC_REG_ADDR 0x0
33#define RTC_MIN_REG_ADDR 0x1
34#define RTC_HR_REG_ADDR 0x2
35#define RTC_DATE_REG_ADDR 0x3
36#define RTC_MON_REG_ADDR 0x4
37#define RTC_YR_REG_ADDR 0x5
38#define RTC_DAY_REG_ADDR 0x6
39#define RTC_STAT_REG_ADDR 0x7
40/*
41 * RTC control register bits
42 */
43
44/*
45 * RTC status register bits
46 */
47#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
48#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
49#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
50#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
51#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
52#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
53
54static uchar rtc_read (uchar reg);
55static void rtc_write (uchar reg, uchar val);
Tor Krill9536dfc2008-03-15 15:40:26 +010056
57/*
58 * Get the current time from the RTC
59 */
60
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030061int rtc_get (struct rtc_time *tmp)
Tor Krill9536dfc2008-03-15 15:40:26 +010062{
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030063 int rel = 0;
Tor Krill9536dfc2008-03-15 15:40:26 +010064 uchar sec, min, hour, mday, wday, mon, year, status;
65
66 status = rtc_read (RTC_STAT_REG_ADDR);
67 sec = rtc_read (RTC_SEC_REG_ADDR);
68 min = rtc_read (RTC_MIN_REG_ADDR);
69 hour = rtc_read (RTC_HR_REG_ADDR);
70 wday = rtc_read (RTC_DAY_REG_ADDR);
71 mday = rtc_read (RTC_DATE_REG_ADDR);
72 mon = rtc_read (RTC_MON_REG_ADDR);
73 year = rtc_read (RTC_YR_REG_ADDR);
74
75 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
76 "hr: %02x min: %02x sec: %02x status: %02x\n",
77 year, mon, mday, wday, hour, min, sec, status);
78
79 if (status & RTC_STAT_BIT_RTCF) {
80 printf ("### Warning: RTC oscillator has stopped\n");
81 rtc_write(RTC_STAT_REG_ADDR,
82 rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030083 rel = -1;
Tor Krill9536dfc2008-03-15 15:40:26 +010084 }
85
86 tmp->tm_sec = bcd2bin (sec & 0x7F);
87 tmp->tm_min = bcd2bin (min & 0x7F);
88 tmp->tm_hour = bcd2bin (hour & 0x3F);
89 tmp->tm_mday = bcd2bin (mday & 0x3F);
90 tmp->tm_mon = bcd2bin (mon & 0x1F);
91 tmp->tm_year = bcd2bin (year)+2000;
92 tmp->tm_wday = bcd2bin (wday & 0x07);
93 tmp->tm_yday = 0;
94 tmp->tm_isdst= 0;
95
96 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
97 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
98 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030099
100 return rel;
Tor Krill9536dfc2008-03-15 15:40:26 +0100101}
102
103/*
104 * Set the RTC
105 */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200106int rtc_set (struct rtc_time *tmp)
Tor Krill9536dfc2008-03-15 15:40:26 +0100107{
108 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
109 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
110 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
111
112 /* enable write */
113 rtc_write(RTC_STAT_REG_ADDR,
114 rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
115
116 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
117 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
118 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
119 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
120 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
121 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
122 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
123
124 /* disable write */
125 rtc_write(RTC_STAT_REG_ADDR,
126 rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200127
128 return 0;
Tor Krill9536dfc2008-03-15 15:40:26 +0100129}
130
131void rtc_reset (void)
132{
133}
134
135/*
136 * Helper functions
137 */
138
139static uchar rtc_read (uchar reg)
140{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
Tor Krill9536dfc2008-03-15 15:40:26 +0100142}
143
144static void rtc_write (uchar reg, uchar val)
145{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
Tor Krill9536dfc2008-03-15 15:40:26 +0100147}