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Dirk Eibachb209a112009-07-17 14:16:40 +02001/*
2 * (C) Copyright 2009
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibachb209a112009-07-17 14:16:40 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibachb209a112009-07-17 14:16:40 +020012#define CONFIG_DLVISION 1 /* on a Neo board */
13
Wolfgang Denk2ae18242010-10-06 09:05:45 +020014#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
Dirk Eibachb209a112009-07-17 14:16:40 +020016/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME dlvision
Dirk Eibach28437152013-06-26 16:04:31 +020020#define CONFIG_IDENT_STRING " dlvision 0.02"
Dirk Eibachb209a112009-07-17 14:16:40 +020021#include "amcc-common.h"
22
23#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
24#define CONFIG_MISC_INIT_R /* call misc_init_r */
25
26#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
27
28/*
29 * Configure PLL
30 */
31#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
32#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
33
34/* new uImage format support */
35#define CONFIG_FIT
36#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibachf9af10d2014-11-13 19:21:12 +010037#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibachb209a112009-07-17 14:16:40 +020038
39#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
40
41/*
42 * Default environment variables
43 */
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 CONFIG_AMCC_DEF_ENV \
46 CONFIG_AMCC_DEF_ENV_POWERPC \
47 CONFIG_AMCC_DEF_ENV_NOR_UPD \
48 "kernel_addr=fc000000\0" \
49 "fdt_addr=fc1e0000\0" \
50 "ramdisk_addr=fc200000\0" \
51 ""
52
53#define CONFIG_PHY_ADDR 4 /* PHY address */
54#define CONFIG_HAS_ETH0
55#define CONFIG_HAS_ETH1
56#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
57#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
58
59/*
60 * Commands additional to the ones defined in amcc-common.h
61 */
Dirk Eibachf9af10d2014-11-13 19:21:12 +010062#define CONFIG_CMD_DTT
63#undef CONFIG_CMD_DHCP
64#undef CONFIG_CMD_DIAG
Dirk Eibachb209a112009-07-17 14:16:40 +020065#undef CONFIG_CMD_EEPROM
Dirk Eibachf9af10d2014-11-13 19:21:12 +010066#undef CONFIG_CMD_I2C
67#undef CONFIG_CMD_IRQ
Dirk Eibachb209a112009-07-17 14:16:40 +020068
69/*
70 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
71 */
72#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
73
74/* SDRAM timings used in datasheet */
75#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
76#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
77#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
78#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
79#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
80
81/*
82 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
83 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
84 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
85 * The Linux BASE_BAUD define should match this configuration.
86 * baseBaud = cpuClock/(uartDivisor*16)
87 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
88 * set Linux BASE_BAUD to 403200.
89 */
Stefan Roese550650d2010-09-20 16:05:31 +020090#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Dirk Eibachb209a112009-07-17 14:16:40 +020091#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
92#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
93#define CONFIG_SYS_BASE_BAUD 691200
94
95/*
96 * I2C stuff
97 */
Dirk Eibach880540d2013-04-25 02:40:01 +000098#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibachb209a112009-07-17 14:16:40 +020099
100/*
101 * FLASH organization
102 */
103#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
104#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
105
106#define CONFIG_SYS_FLASH_BASE 0xFC000000
107#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
108
109#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
110#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
111
112#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
113#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
114
115#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibachb209a112009-07-17 14:16:40 +0200116
117#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
118#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
119
120#ifdef CONFIG_ENV_IS_IN_FLASH
121#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
122#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
123#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
124
125/* Address and size of Redundant Environment Sector */
126#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
127#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
128#endif
129
130/*
131 * PPC405 GPIO Configuration
132 */
133#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
134{ \
135/* GPIO Core 0 */ \
136{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
137{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
138{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
139{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
140{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
141{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
142{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
143{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
144{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
145{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
146{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
147{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
148{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
149{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
150{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
151{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
152{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
153{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
154{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
155{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
156{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
157{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
158{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
159{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
160{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
161{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
162{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
164{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
166{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
167{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
168} \
169}
170
171/*
172 * Definitions for initial stack pointer and data area (in data cache)
173 */
174/* use on chip memory (OCM) for temperary stack until sdram is tested */
175#define CONFIG_SYS_TEMP_STACK_OCM 1
176
177/* On Chip Memory location */
178#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
179#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
180#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200181#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
Dirk Eibachb209a112009-07-17 14:16:40 +0200182
Dirk Eibachb209a112009-07-17 14:16:40 +0200183#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200184 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibachb209a112009-07-17 14:16:40 +0200185#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
186
187/*
188 * External Bus Controller (EBC) Setup
189 */
190
191/* Memory Bank 0 (NOR-FLASH) initialization */
192#define CONFIG_SYS_EBC_PB0AP 0x92015480
193/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
194#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
195
196/* Memory Bank 1 (NVRAM) initializatio */
197#define CONFIG_SYS_EBC_PB1AP 0x92015480
198/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
199#define CONFIG_SYS_EBC_PB1CR 0xFB858000
200
201/* Memory Bank 2 (UART) initialization */
202#define CONFIG_UART_BASE 0x7f100000
203#define CONFIG_SYS_EBC_PB2AP 0x92015480
204/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
205#define CONFIG_SYS_EBC_PB2CR 0x7f118000
206
207/* Memory Bank 3 (Latches) initialization */
208#define CONFIG_SYS_LATCH_BASE 0x7f200000
209#define CONFIG_SYS_EBC_PB3AP 0x92015480
210/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
211#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
212
213#endif /* __CONFIG_H */