blob: 96b357b6fd4f25380f17d60820c4775f652c7458 [file] [log] [blame]
Peter Tyser5da6f802009-06-30 17:26:01 -05001/*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Peter Tyser5da6f802009-06-30 17:26:01 -05006 */
7
8/*
Peter Tyserc00ac252010-10-22 00:20:26 -05009 * xpedite517x board configuration file
Peter Tyser5da6f802009-06-30 17:26:01 -050010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
Peter Tyser5da6f802009-06-30 17:26:01 -050017#define CONFIG_MPC8641 1 /* MPC8641 specific */
18#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
19#define CONFIG_SYS_BOARD_NAME "XPedite5170"
John Schmoller92af65492010-10-22 00:20:24 -050020#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyser5da6f802009-06-30 17:26:01 -050021#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050023#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Peter Tyser5da6f802009-06-30 17:26:01 -050024#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
25#define CONFIG_ALTIVEC 1
John Schmoller02851002015-01-09 15:42:50 -060026#define CONFIG_DISPLAY_BOARDINFO
Peter Tyser5da6f802009-06-30 17:26:01 -050027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xfff00000
29
Peter Tyser5da6f802009-06-30 17:26:01 -050030#define CONFIG_PCI 1 /* Enable PCI/PCIE */
31#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
32#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
33#define CONFIG_PCIE1 1 /* PCIE controler 1 */
34#define CONFIG_PCIE2 1 /* PCIE controler 2 */
35#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000036#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Peter Tyser5da6f802009-06-30 17:26:01 -050037#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
38#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
39
40/*
41 * DDR config
42 */
York Sun5614e712013-09-30 09:22:09 -070043#define CONFIG_SYS_FSL_DDR2
Peter Tyser5da6f802009-06-30 17:26:01 -050044#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45#define CONFIG_DDR_SPD
46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
48#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
49#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
50#define CONFIG_NUM_DDR_CONTROLLERS 2
51#define CONFIG_DIMM_SLOTS_PER_CTLR 1
52#define CONFIG_CHIP_SELECTS_PER_CTRL 1
53#define CONFIG_DDR_ECC
54#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
55#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
56#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
57#define CONFIG_VERY_BIG_RAM
58#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
59
60/*
61 * virtual address to be used for temporary mappings. There
62 * should be 128k free at this VA.
63 */
64#define CONFIG_SYS_SCRATCH_VA 0xe0000000
65
66#ifndef __ASSEMBLY__
67extern unsigned long get_board_sys_clk(unsigned long dummy);
68#endif
69
70#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
71
72/*
73 * L2CR setup
74 */
75#define CONFIG_SYS_L2
76#define L2_INIT 0
77#define L2_ENABLE (L2CR_L2E)
78
79/*
80 * Base addresses -- Note these are effective addresses where the
81 * actual resources get mapped (not physical addresses)
82 */
83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
84#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
85#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
86#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
87#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
88#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
Peter Tyser5da6f802009-06-30 17:26:01 -050089
90/*
91 * Diagnostics
92 */
93#define CONFIG_SYS_ALT_MEMTEST
94#define CONFIG_SYS_MEMTEST_START 0x10000000
95#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -050096#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
97 CONFIG_SYS_POST_I2C)
98#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
99 CONFIG_SYS_I2C_DS4510_ADDR, \
100 CONFIG_SYS_I2C_EEPROM_ADDR, \
101 CONFIG_SYS_I2C_LM90_ADDR, \
102 CONFIG_SYS_I2C_PCA9553_ADDR, \
103 CONFIG_SYS_I2C_PCA953X_ADDR0, \
104 CONFIG_SYS_I2C_PCA953X_ADDR1, \
105 CONFIG_SYS_I2C_PCA953X_ADDR2, \
106 CONFIG_SYS_I2C_PCA953X_ADDR3, \
107 CONFIG_SYS_I2C_PEX8518_ADDR, \
108 CONFIG_SYS_I2C_RTC_ADDR}
109/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
110#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyser5da6f802009-06-30 17:26:01 -0500111
112/*
113 * Memory map
114 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
115 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
116 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
117 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
118 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
119 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
120 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
121 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
122 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
123 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
124 */
125
Kumar Gala202d9482009-09-15 22:21:58 -0500126#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
Peter Tyser5da6f802009-06-30 17:26:01 -0500127
128/*
129 * NAND flash configuration
130 */
131#define CONFIG_SYS_NAND_BASE 0xef800000
132#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
133#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
134#define CONFIG_SYS_MAX_NAND_DEVICE 2
135#define CONFIG_NAND_ACTL
136#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
137#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
138#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
139#define CONFIG_SYS_NAND_ACTL_DELAY 25
Peter Tyser5da6f802009-06-30 17:26:01 -0500140#define CONFIG_JFFS2_NAND
141
142/*
143 * NOR flash configuration
144 */
145#define CONFIG_SYS_FLASH_BASE 0xf8000000
146#define CONFIG_SYS_FLASH_BASE2 0xf0000000
147#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
149#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
150#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
152#define CONFIG_FLASH_CFI_DRIVER
153#define CONFIG_SYS_FLASH_CFI
154#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
156 {0xf7f00000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyser5da6f802009-06-30 17:26:01 -0500158#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
159
160/*
161 * Chip select configuration
162 */
163/* NOR Flash 0 on CS0 */
164#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
165 BR_PS_16 |\
166 BR_V)
167#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
168 OR_GPCM_CSNT |\
169 OR_GPCM_XACS |\
170 OR_GPCM_ACS_DIV2 |\
171 OR_GPCM_SCY_8 |\
172 OR_GPCM_TRLX |\
173 OR_GPCM_EHTR |\
174 OR_GPCM_EAD)
175
176/* NOR Flash 1 on CS1 */
177#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
178 BR_PS_16 |\
179 BR_V)
180#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
181
182/* NAND flash on CS2 */
183#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
184 BR_PS_8 |\
185 BR_V)
186#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
187 OR_GPCM_BCTLD |\
188 OR_GPCM_CSNT |\
189 OR_GPCM_ACS_DIV4 |\
190 OR_GPCM_SCY_4 |\
191 OR_GPCM_TRLX |\
192 OR_GPCM_EHTR)
193
194/* Optional NAND flash on CS3 */
195#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
196 BR_PS_8 |\
197 BR_V)
198#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
199
200/*
201 * Use L1 as initial stack
202 */
203#define CONFIG_SYS_INIT_RAM_LOCK 1
204#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200205#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyser5da6f802009-06-30 17:26:01 -0500206
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200207#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyser5da6f802009-06-30 17:26:01 -0500208#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
211#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
212
213/*
214 * Serial Port
215 */
216#define CONFIG_CONS_INDEX 1
Peter Tyser5da6f802009-06-30 17:26:01 -0500217#define CONFIG_SYS_NS16550_SERIAL
218#define CONFIG_SYS_NS16550_REG_SIZE 1
219#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
221#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
222#define CONFIG_SYS_BAUDRATE_TABLE \
223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
224#define CONFIG_BAUDRATE 115200
225#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
226#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
227
228/*
229 * Use the HUSH parser
230 */
231#define CONFIG_SYS_HUSH_PARSER
Peter Tyser5da6f802009-06-30 17:26:01 -0500232
233/*
234 * Pass open firmware flat tree
235 */
236#define CONFIG_OF_LIBFDT 1
237#define CONFIG_OF_BOARD_SETUP 1
238#define CONFIG_OF_STDOUT_VIA_ALIAS 1
239
Peter Tyser5da6f802009-06-30 17:26:01 -0500240/*
241 * I2C
242 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200243#define CONFIG_SYS_I2C
244#define CONFIG_SYS_I2C_FSL
245#define CONFIG_SYS_FSL_I2C_SPEED 100000
246#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
247#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
248#define CONFIG_SYS_FSL_I2C2_SPEED 100000
249#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
250#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Peter Tyser5da6f802009-06-30 17:26:01 -0500251
252/* PEX8518 slave I2C interface */
253#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
254
255/* I2C DS1631 temperature sensor */
256#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
257#define CONFIG_DTT_DS1621
258#define CONFIG_DTT_SENSORS { 0 }
Peter Tyser66a8b442010-10-22 00:20:33 -0500259#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyser5da6f802009-06-30 17:26:01 -0500260
261/* I2C EEPROM - AT24C128B */
262#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
263#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
264#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
265#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
266
267/* I2C RTC */
268#define CONFIG_RTC_M41T11 1
269#define CONFIG_SYS_I2C_RTC_ADDR 0x68
270#define CONFIG_SYS_M41T11_BASE_YEAR 2000
271
272/* GPIO/EEPROM/SRAM */
273#define CONFIG_DS4510
274#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
275
276/* GPIO */
277#define CONFIG_PCA953X
278#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
279#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
280#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
281#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
282#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
Peter Tyser66a8b442010-10-22 00:20:33 -0500283#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
Peter Tyser5da6f802009-06-30 17:26:01 -0500284
285/*
286 * PU = pulled high, PD = pulled low
287 * I = input, O = output, IO = input/output
288 */
289/* PCA9557 @ 0x18*/
290#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
291#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
292#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
293#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
294#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
295#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
296
297/* PCA9557 @ 0x1c*/
298#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
299#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
300#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
301#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
302#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
303#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
304#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
305#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
306
307/* PCA9557 @ 0x1e*/
308#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
309#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
310#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
311#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
312#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
313#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
314#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
315
316/* PCA9557 @ 0x1f */
317#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
318#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
319#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
320#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
321
322/*
323 * General PCI
324 * Memory space is mapped 1-1, but I/O space must start from 0.
325 */
326/* PCIE1 - PEX8518 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500327#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
328#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500329#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500330#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500331#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
332#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
333
334/* PCIE2 - VPX P1 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500335#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
336#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500337#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500338#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500339#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
340#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
341
342/*
343 * Networking options
344 */
345#define CONFIG_TSEC_ENET /* tsec ethernet support */
346#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Peter Tyser5da6f802009-06-30 17:26:01 -0500347#define CONFIG_MII 1 /* MII PHY management */
348#define CONFIG_ETHPRIME "eTSEC1"
349
350#define CONFIG_TSEC1 1
351#define CONFIG_TSEC1_NAME "eTSEC1"
352#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353#define TSEC1_PHY_ADDR 1
354#define TSEC1_PHYIDX 0
355#define CONFIG_HAS_ETH0
356
357#define CONFIG_TSEC2 1
358#define CONFIG_TSEC2_NAME "eTSEC2"
359#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
360#define TSEC2_PHY_ADDR 2
361#define TSEC2_PHYIDX 0
362#define CONFIG_HAS_ETH1
363
364/*
365 * BAT mappings
366 */
367#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
368#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
369 BATL_PP_RW |\
370 BATL_CACHEINHIBIT |\
371 BATL_GUARDEDSTORAGE)
372#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
373 BATU_BL_1M |\
374 BATU_VS |\
375 BATU_VP)
376#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
377 BATL_PP_RW |\
378 BATL_CACHEINHIBIT)
379#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
380#endif
381
382/*
383 * BAT0 2G Cacheable, non-guarded
384 * 0x0000_0000 2G DDR
385 */
386#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
387#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
388#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
389#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
390
391/*
392 * BAT1 1G Cache-inhibited, guarded
393 * 0x8000_0000 1G PCI-Express 1 Memory
394 */
395#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
396 BATL_PP_RW |\
397 BATL_CACHEINHIBIT |\
398 BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
400 BATU_BL_1G |\
401 BATU_VS |\
402 BATU_VP)
403#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
404 BATL_PP_RW |\
405 BATL_CACHEINHIBIT)
406#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
407
408/*
409 * BAT2 512M Cache-inhibited, guarded
410 * 0xc000_0000 512M PCI-Express 2 Memory
411 */
412#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
413 BATL_PP_RW |\
414 BATL_CACHEINHIBIT |\
415 BATL_GUARDEDSTORAGE)
416#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
417 BATU_BL_512M |\
418 BATU_VS |\
419 BATU_VP)
420#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
421 BATL_PP_RW |\
422 BATL_CACHEINHIBIT)
423#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
424
425/*
426 * BAT3 1M Cache-inhibited, guarded
427 * 0xe000_0000 1M CCSR
428 */
429#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
430 BATL_PP_RW |\
431 BATL_CACHEINHIBIT |\
432 BATL_GUARDEDSTORAGE)
433#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
434 BATU_BL_1M |\
435 BATU_VS |\
436 BATU_VP)
437#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
438 BATL_PP_RW |\
439 BATL_CACHEINHIBIT)
440#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
441
442/*
443 * BAT4 32M Cache-inhibited, guarded
444 * 0xe200_0000 16M PCI-Express 1 I/O
445 * 0xe300_0000 16M PCI-Express 2 I/0
446 */
447#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
448 BATL_PP_RW |\
449 BATL_CACHEINHIBIT |\
450 BATL_GUARDEDSTORAGE)
451#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
452 BATU_BL_32M |\
453 BATU_VS |\
454 BATU_VP)
455#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
456 BATL_PP_RW |\
457 BATL_CACHEINHIBIT)
458#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
459
460/*
461 * BAT5 128K Cacheable, non-guarded
462 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
463 */
464#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
465 BATL_PP_RW |\
466 BATL_MEMCOHERENCE)
467#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
468 BATU_BL_128K |\
469 BATU_VS |\
470 BATU_VP)
471#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
472#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
473
474/*
475 * BAT6 256M Cache-inhibited, guarded
476 * 0xf000_0000 256M FLASH
477 */
478#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
479 BATL_PP_RW |\
480 BATL_CACHEINHIBIT |\
481 BATL_GUARDEDSTORAGE)
482#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
483 BATU_BL_256M |\
484 BATU_VS |\
485 BATU_VP)
486#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
487 BATL_PP_RW |\
488 BATL_MEMCOHERENCE)
489#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
490
491/* Map the last 1M of flash where we're running from reset */
492#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
493 BATL_PP_RW |\
494 BATL_CACHEINHIBIT |\
495 BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200496#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
Peter Tyser5da6f802009-06-30 17:26:01 -0500497 BATU_BL_1M |\
498 BATU_VS |\
499 BATU_VP)
500#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
501 BATL_PP_RW |\
502 BATL_MEMCOHERENCE)
503#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
504
505/*
506 * BAT7 64M Cache-inhibited, guarded
507 * 0xe800_0000 64K NAND FLASH
508 * 0xe804_0000 128K DUART Registers
509 */
510#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
511 BATL_PP_RW |\
512 BATL_CACHEINHIBIT |\
513 BATL_GUARDEDSTORAGE)
514#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
515 BATU_BL_512K |\
516 BATU_VS |\
517 BATU_VP)
518#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
519 BATL_PP_RW |\
520 BATL_CACHEINHIBIT)
521#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
522
523/*
524 * Command configuration.
525 */
Peter Tyser5da6f802009-06-30 17:26:01 -0500526#define CONFIG_CMD_ASKENV
527#define CONFIG_CMD_DATE
528#define CONFIG_CMD_DHCP
529#define CONFIG_CMD_DS4510
530#define CONFIG_CMD_DS4510_INFO
531#define CONFIG_CMD_DTT
532#define CONFIG_CMD_EEPROM
Peter Tyser5da6f802009-06-30 17:26:01 -0500533#define CONFIG_CMD_I2C
534#define CONFIG_CMD_IRQ
535#define CONFIG_CMD_JFFS2
536#define CONFIG_CMD_MII
537#define CONFIG_CMD_NAND
Peter Tyser5da6f802009-06-30 17:26:01 -0500538#define CONFIG_CMD_PCA953X
539#define CONFIG_CMD_PCA953X_INFO
540#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500541#define CONFIG_CMD_PCI_ENUM
Peter Tyser5da6f802009-06-30 17:26:01 -0500542#define CONFIG_CMD_PING
543#define CONFIG_CMD_REGINFO
544#define CONFIG_CMD_SNTP
545
546/*
547 * Miscellaneous configurable options
548 */
549#define CONFIG_SYS_LONGHELP /* undef to save memory */
550#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Peter Tyser5da6f802009-06-30 17:26:01 -0500551#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
552#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
553#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
554#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500555#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
556#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
557#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
558#define CONFIG_PANIC_HANG /* do not reset board on panic */
559#define CONFIG_PREBOOT /* enable preboot variable */
560#define CONFIG_FIT 1
561#define CONFIG_FIT_VERBOSE 1
562#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
563
564/*
565 * For booting Linux, the board info and command line data
566 * have to be in the first 16 MB of memory, since this is
567 * the maximum mapped by the Linux kernel during initialization.
568 */
569#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500570#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500571
572/*
Peter Tyser5da6f802009-06-30 17:26:01 -0500573 * Environment Configuration
574 */
575#define CONFIG_ENV_IS_IN_FLASH 1
576#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
577#define CONFIG_ENV_SIZE 0x8000
578#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
579
580/*
581 * Flash memory map:
582 * fffc0000 - ffffffff Pri FDT (256KB)
583 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
584 * fff00000 - fff7ffff Pri U-Boot (512 KB)
585 * fef00000 - ffefffff Pri OS image (16MB)
586 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
587 *
588 * f7fc0000 - f7ffffff Sec FDT (256KB)
589 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
590 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
591 * f6f00000 - f7efffff Sec OS image (16MB)
592 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
593 */
Marek Vasut5368c552012-09-23 17:41:24 +0200594#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
595#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
596#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
597#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
598#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
599#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
Peter Tyser5da6f802009-06-30 17:26:01 -0500600
601#define CONFIG_PROG_UBOOT1 \
602 "$download_cmd $loadaddr $ubootfile; " \
603 "if test $? -eq 0; then " \
604 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
605 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
606 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
607 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
608 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
609 "if test $? -ne 0; then " \
610 "echo PROGRAM FAILED; " \
611 "else; " \
612 "echo PROGRAM SUCCEEDED; " \
613 "fi; " \
614 "else; " \
615 "echo DOWNLOAD FAILED; " \
616 "fi;"
617
618#define CONFIG_PROG_UBOOT2 \
619 "$download_cmd $loadaddr $ubootfile; " \
620 "if test $? -eq 0; then " \
621 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
622 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
623 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
624 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
625 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
626 "if test $? -ne 0; then " \
627 "echo PROGRAM FAILED; " \
628 "else; " \
629 "echo PROGRAM SUCCEEDED; " \
630 "fi; " \
631 "else; " \
632 "echo DOWNLOAD FAILED; " \
633 "fi;"
634
635#define CONFIG_BOOT_OS_NET \
636 "$download_cmd $osaddr $osfile; " \
637 "if test $? -eq 0; then " \
638 "if test -n $fdtaddr; then " \
639 "$download_cmd $fdtaddr $fdtfile; " \
640 "if test $? -eq 0; then " \
641 "bootm $osaddr - $fdtaddr; " \
642 "else; " \
643 "echo FDT DOWNLOAD FAILED; " \
644 "fi; " \
645 "else; " \
646 "bootm $osaddr; " \
647 "fi; " \
648 "else; " \
649 "echo OS DOWNLOAD FAILED; " \
650 "fi;"
651
652#define CONFIG_PROG_OS1 \
653 "$download_cmd $osaddr $osfile; " \
654 "if test $? -eq 0; then " \
655 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
656 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
657 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
658 "if test $? -ne 0; then " \
659 "echo OS PROGRAM FAILED; " \
660 "else; " \
661 "echo OS PROGRAM SUCCEEDED; " \
662 "fi; " \
663 "else; " \
664 "echo OS DOWNLOAD FAILED; " \
665 "fi;"
666
667#define CONFIG_PROG_OS2 \
668 "$download_cmd $osaddr $osfile; " \
669 "if test $? -eq 0; then " \
670 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
671 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
672 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
673 "if test $? -ne 0; then " \
674 "echo OS PROGRAM FAILED; " \
675 "else; " \
676 "echo OS PROGRAM SUCCEEDED; " \
677 "fi; " \
678 "else; " \
679 "echo OS DOWNLOAD FAILED; " \
680 "fi;"
681
682#define CONFIG_PROG_FDT1 \
683 "$download_cmd $fdtaddr $fdtfile; " \
684 "if test $? -eq 0; then " \
685 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
686 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
687 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
688 "if test $? -ne 0; then " \
689 "echo FDT PROGRAM FAILED; " \
690 "else; " \
691 "echo FDT PROGRAM SUCCEEDED; " \
692 "fi; " \
693 "else; " \
694 "echo FDT DOWNLOAD FAILED; " \
695 "fi;"
696
697#define CONFIG_PROG_FDT2 \
698 "$download_cmd $fdtaddr $fdtfile; " \
699 "if test $? -eq 0; then " \
700 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
701 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
702 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
703 "if test $? -ne 0; then " \
704 "echo FDT PROGRAM FAILED; " \
705 "else; " \
706 "echo FDT PROGRAM SUCCEEDED; " \
707 "fi; " \
708 "else; " \
709 "echo FDT DOWNLOAD FAILED; " \
710 "fi;"
711
712#define CONFIG_EXTRA_ENV_SETTINGS \
713 "autoload=yes\0" \
714 "download_cmd=tftp\0" \
715 "console_args=console=ttyS0,115200\0" \
716 "root_args=root=/dev/nfs rw\0" \
717 "misc_args=ip=on\0" \
718 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
719 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500720 "osfile=/home/user/board.uImage\0" \
721 "fdtfile=/home/user/board.dtb\0" \
Peter Tyser5da6f802009-06-30 17:26:01 -0500722 "ubootfile=/home/user/u-boot.bin\0" \
723 "fdtaddr=c00000\0" \
724 "osaddr=0x1000000\0" \
725 "loadaddr=0x1000000\0" \
726 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
727 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
728 "prog_os1="CONFIG_PROG_OS1"\0" \
729 "prog_os2="CONFIG_PROG_OS2"\0" \
730 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
731 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
732 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
733 "bootcmd_flash1=run set_bootargs; " \
734 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
735 "bootcmd_flash2=run set_bootargs; " \
736 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
737 "bootcmd=run bootcmd_flash1\0"
738#endif /* __CONFIG_H */