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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +02002/*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +02004 */
5
Olliver Schinagl048447c2018-11-21 20:05:27 +02006#include <linux/bitops.h>
7
Paul Kocialkowski940382f2015-03-22 18:08:21 +01008enum axp209_reg {
9 AXP209_POWER_STATUS = 0x00,
10 AXP209_CHIP_VERSION = 0x03,
Hans de Goedebeba4012015-10-04 12:01:17 +020011 AXP209_OUTPUT_CTRL = 0x12,
Paul Kocialkowski940382f2015-03-22 18:08:21 +010012 AXP209_DCDC2_VOLTAGE = 0x23,
Olliver Schinagl61436d52018-11-21 20:05:30 +020013 AXP209_VRC_DCDC2_LDO3 = 0x25,
Paul Kocialkowski940382f2015-03-22 18:08:21 +010014 AXP209_DCDC3_VOLTAGE = 0x27,
15 AXP209_LDO24_VOLTAGE = 0x28,
16 AXP209_LDO3_VOLTAGE = 0x29,
17 AXP209_IRQ_ENABLE1 = 0x40,
18 AXP209_IRQ_ENABLE2 = 0x41,
19 AXP209_IRQ_ENABLE3 = 0x42,
20 AXP209_IRQ_ENABLE4 = 0x43,
21 AXP209_IRQ_ENABLE5 = 0x44,
22 AXP209_IRQ_STATUS5 = 0x4c,
23 AXP209_SHUTDOWN = 0x32,
Paul Kocialkowski940382f2015-03-22 18:08:21 +010024};
25
Olliver Schinagl048447c2018-11-21 20:05:27 +020026#define AXP209_POWER_STATUS_ON_BY_DC BIT(0)
27#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010028
Olliver Schinaglf5eebc72018-11-21 20:05:28 +020029#define AXP209_CHIP_VERSION_MASK 0x0f
30
Olliver Schinagl048447c2018-11-21 20:05:27 +020031#define AXP209_OUTPUT_CTRL_EXTEN BIT(0)
32#define AXP209_OUTPUT_CTRL_DCDC3 BIT(1)
33#define AXP209_OUTPUT_CTRL_LDO2 BIT(2)
34#define AXP209_OUTPUT_CTRL_LDO4 BIT(3)
35#define AXP209_OUTPUT_CTRL_DCDC2 BIT(4)
36#define AXP209_OUTPUT_CTRL_LDO3 BIT(6)
Hans de Goedebeba4012015-10-04 12:01:17 +020037
Olliver Schinagl61436d52018-11-21 20:05:30 +020038/*
39 * AXP209 datasheet contains wrong information about LDO3 VRC:
40 * - VRC is actually enabled when BIT(1) is True
41 * - VRC is actually not enabled by default (BIT(3) = 0 after reset)
42 */
43#define AXP209_VRC_LDO3_EN BIT(3)
44#define AXP209_VRC_DCDC2_EN BIT(2)
45#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN)
46#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN
47#define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN)
48#define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN
49#define AXP209_VRC_LDO3_MASK 0xa
50#define AXP209_VRC_DCDC2_MASK 0x5
51#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \
52 (((reg) & ~AXP209_VRC_DCDC2_MASK) | \
53 ((cfg) & AXP209_VRC_DCDC2_MASK))
54#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \
55 (((reg) & ~AXP209_VRC_LDO3_MASK) | \
56 ((cfg) & AXP209_VRC_LDO3_MASK))
57
Olliver Schinagl3f7d76a2018-11-21 20:05:29 +020058#define AXP209_LDO24_LDO2_MASK 0xf0
59#define AXP209_LDO24_LDO4_MASK 0x0f
60#define AXP209_LDO24_LDO2_SET(reg, cfg) \
61 (((reg) & ~AXP209_LDO24_LDO2_MASK) | \
62 (((cfg) << 4) & AXP209_LDO24_LDO2_MASK))
63#define AXP209_LDO24_LDO4_SET(reg, cfg) \
64 (((reg) & ~AXP209_LDO24_LDO4_MASK) | \
65 (((cfg) << 0) & AXP209_LDO24_LDO4_MASK))
66
67#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN BIT(7)
68#define AXP209_LDO3_VOLTAGE_MASK 0x7f
69#define AXP209_LDO3_VOLTAGE_SET(x) ((x) & AXP209_LDO3_VOLTAGE_MASK)
70
Olliver Schinagl048447c2018-11-21 20:05:27 +020071#define AXP209_IRQ5_PEK_UP BIT(6)
72#define AXP209_IRQ5_PEK_DOWN BIT(5)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010073
Olliver Schinagl048447c2018-11-21 20:05:27 +020074#define AXP209_POWEROFF BIT(7)
Paul Kocialkowski940382f2015-03-22 18:08:21 +010075
Hans de Goede2fcf0332015-04-25 17:25:14 +020076/* For axp_gpio.c */
Samuel Holland344df3c2021-08-22 18:18:04 -050077#ifdef CONFIG_AXP209_POWER
Hans de Goede2fcf0332015-04-25 17:25:14 +020078#define AXP_POWER_STATUS 0x00
Andre Przywara78592c02022-01-21 13:37:31 +000079#define AXP_POWER_STATUS_ALDO_IN BIT(0)
Hans de Goede2fcf0332015-04-25 17:25:14 +020080#define AXP_GPIO0_CTRL 0x90
81#define AXP_GPIO1_CTRL 0x92
82#define AXP_GPIO2_CTRL 0x93
Olliver Schinagl048447c2018-11-21 20:05:27 +020083#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
84#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
85#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
Hans de Goede2fcf0332015-04-25 17:25:14 +020086#define AXP_GPIO_STATE 0x94
Olliver Schinagl048447c2018-11-21 20:05:27 +020087#define AXP_GPIO_STATE_OFFSET 4
Samuel Holland344df3c2021-08-22 18:18:04 -050088#endif