Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <fdtdec.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 9 | #include <asm/io.h> |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 10 | #include <asm/ptrace.h> |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 11 | #include <asm/arch/cpu.h> |
| 12 | #include <asm/arch/soc.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 14 | |
Marek BehĂșn | 4b8cb84 | 2018-08-17 12:58:51 +0200 | [diff] [blame] | 15 | #include "comphy_core.h" |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 16 | #include "comphy_hpipe.h" |
| 17 | #include "sata.h" |
| 18 | #include "utmi_phy.h" |
| 19 | |
| 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
| 22 | #define SD_ADDR(base, lane) (base + 0x1000 * lane) |
| 23 | #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) |
| 24 | #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) |
| 25 | |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 26 | /* Firmware related definitions used for SMC calls */ |
| 27 | #define MV_SIP_COMPHY_POWER_ON 0x82000001 |
| 28 | #define MV_SIP_COMPHY_POWER_OFF 0x82000002 |
| 29 | #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 |
| 30 | |
| 31 | #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) |
| 32 | #define COMPHY_FW_FORMAT(mode, idx, speeds) \ |
| 33 | (((mode) << 12) | ((idx) << 8) | ((speeds) << 2)) |
| 34 | #define COMPHY_SATA_MODE 0x1 |
| 35 | #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ |
| 36 | #define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ |
| 37 | #define COMPHY_USB3H_MODE 0x4 |
| 38 | #define COMPHY_USB3D_MODE 0x5 |
| 39 | #define COMPHY_PCIE_MODE 0x6 |
| 40 | #define COMPHY_RXAUI_MODE 0x7 |
| 41 | #define COMPHY_XFI_MODE 0x8 |
| 42 | #define COMPHY_SFI_MODE 0x9 |
| 43 | #define COMPHY_USB3_MODE 0xa |
| 44 | #define COMPHY_AP_MODE 0xb |
| 45 | |
| 46 | /* Comphy unit index macro */ |
| 47 | #define COMPHY_UNIT_ID0 0 |
| 48 | #define COMPHY_UNIT_ID1 1 |
| 49 | #define COMPHY_UNIT_ID2 2 |
| 50 | #define COMPHY_UNIT_ID3 3 |
| 51 | |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 52 | struct utmi_phy_data { |
| 53 | void __iomem *utmi_base_addr; |
| 54 | void __iomem *usb_cfg_addr; |
| 55 | void __iomem *utmi_cfg_addr; |
| 56 | u32 utmi_phy_port; |
| 57 | }; |
| 58 | |
| 59 | /* |
| 60 | * For CP-110 we have 2 Selector registers "PHY Selectors", |
| 61 | * and "PIPE Selectors". |
| 62 | * PIPE selector include USB and PCIe options. |
| 63 | * PHY selector include the Ethernet and SATA options, every Ethernet |
| 64 | * option has different options, for example: serdes lane2 had option |
Stefan Roese | e7ed957 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 65 | * Eth_port_0 that include (SGMII0, RXAUI0, SFI) |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 66 | */ |
| 67 | struct comphy_mux_data cp110_comphy_phy_mux_data[] = { |
Stefan Roese | fdc9e88 | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 68 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ |
| 69 | {PHY_TYPE_SATA1, 0x4} } }, |
| 70 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ |
| 71 | {PHY_TYPE_SATA0, 0x4} } }, |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 72 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ |
Stefan Roese | fdc9e88 | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 73 | {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, |
| 74 | {PHY_TYPE_SATA0, 0x4} } }, |
| 75 | {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ |
| 76 | {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, |
Stefan Roese | e7ed957 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 77 | {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ |
Stefan Roese | fdc9e88 | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 78 | {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, |
Stefan Roese | e7ed957 | 2017-04-24 18:45:29 +0300 | [diff] [blame] | 79 | {PHY_TYPE_SGMII1, 0x1} } }, |
Stefan Roese | fdc9e88 | 2017-04-24 18:45:27 +0300 | [diff] [blame] | 80 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ |
| 81 | {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { |
| 85 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ |
| 86 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ |
| 87 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, |
| 88 | {PHY_TYPE_PEX0, 0x4} } }, |
| 89 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ |
| 90 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, |
| 91 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ |
| 92 | {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, |
| 93 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ |
| 94 | {PHY_TYPE_USB3_HOST1, 0x1}, |
| 95 | {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, |
| 96 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ |
| 97 | }; |
| 98 | |
| 99 | static u32 polling_with_timeout(void __iomem *addr, u32 val, |
| 100 | u32 mask, unsigned long usec_timout) |
| 101 | { |
| 102 | u32 data; |
| 103 | |
| 104 | do { |
| 105 | udelay(1); |
| 106 | data = readl(addr) & mask; |
| 107 | } while (data != val && --usec_timout > 0); |
| 108 | |
| 109 | if (usec_timout == 0) |
| 110 | return data; |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
Stefan Roese | 7dda98e | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 115 | static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, |
| 116 | bool is_end_point, void __iomem *hpipe_base, |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 117 | void __iomem *comphy_base) |
| 118 | { |
| 119 | u32 mask, data, ret = 1; |
| 120 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 121 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 122 | void __iomem *addr; |
| 123 | u32 pcie_clk = 0; /* set input by default */ |
| 124 | |
| 125 | debug_enter(); |
| 126 | |
| 127 | /* |
| 128 | * ToDo: |
| 129 | * Add SAR (Sample-At-Reset) configuration for the PCIe clock |
| 130 | * direction. SAR code is currently not ported from Marvell |
| 131 | * U-Boot to mainline version. |
| 132 | * |
| 133 | * SerDes Lane 4/5 got the PCIe ref-clock #1, |
| 134 | * and SerDes Lane 0 got PCIe ref-clock #0 |
| 135 | */ |
| 136 | debug("PCIe clock = %x\n", pcie_clk); |
Stefan Roese | 7dda98e | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 137 | debug("PCIe RC = %d\n", !is_end_point); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 138 | debug("PCIe width = %d\n", pcie_width); |
| 139 | |
| 140 | /* enable PCIe by4 and by2 */ |
| 141 | if (lane == 0) { |
| 142 | if (pcie_width == 4) { |
| 143 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 144 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, |
| 145 | COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); |
| 146 | } else if (pcie_width == 2) { |
| 147 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 148 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, |
| 149 | COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * If PCIe clock is output and clock source from SerDes lane 5, |
| 155 | * we need to configure the clock-source MUX. |
| 156 | * By default, the clock source is from lane 4 |
| 157 | */ |
| 158 | if (pcie_clk && clk_src && (lane == 5)) { |
| 159 | reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, |
| 160 | 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, |
| 161 | DFX_DEV_GEN_PCIE_CLK_SRC_MASK); |
| 162 | } |
| 163 | |
| 164 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 165 | /* RFU configurations - hard reset comphy */ |
| 166 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 167 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 168 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 169 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 170 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 171 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 172 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 173 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 174 | mask |= COMMON_PHY_PHY_MODE_MASK; |
| 175 | data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; |
| 176 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 177 | |
| 178 | /* release from hard reset */ |
| 179 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 180 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 181 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 182 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 183 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 184 | |
| 185 | /* Wait 1ms - until band gap and ref clock ready */ |
| 186 | mdelay(1); |
| 187 | /* Start comphy Configuration */ |
| 188 | debug("stage: Comphy configuration\n"); |
| 189 | /* Set PIPE soft reset */ |
| 190 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; |
| 191 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; |
| 192 | /* Set PHY datapath width mode for V0 */ |
| 193 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; |
| 194 | data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; |
| 195 | /* Set Data bus width USB mode for V0 */ |
| 196 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; |
| 197 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; |
| 198 | /* Set CORE_CLK output frequency for 250Mhz */ |
| 199 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; |
| 200 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; |
| 201 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); |
| 202 | /* Set PLL ready delay for 0x2 */ |
| 203 | data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; |
| 204 | mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; |
| 205 | if (pcie_width != 1) { |
| 206 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; |
| 207 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; |
| 208 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; |
| 209 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; |
| 210 | } |
| 211 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); |
| 212 | |
| 213 | /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ |
| 214 | data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; |
| 215 | mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; |
| 216 | if (pcie_width != 1) { |
| 217 | mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; |
| 218 | mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; |
| 219 | mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; |
| 220 | if (lane == 0) { |
| 221 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; |
| 222 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; |
| 223 | } else if (lane == (pcie_width - 1)) { |
| 224 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; |
| 225 | } |
| 226 | } |
| 227 | reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); |
| 228 | /* Config update polarity equalization */ |
| 229 | reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, |
| 230 | 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, |
| 231 | HPIPE_CFG_UPDATE_POLARITY_MASK); |
| 232 | /* Set PIPE version 4 to mode enable */ |
| 233 | reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, |
| 234 | 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, |
| 235 | HPIPE_DFE_CTRL_28_PIPE4_MASK); |
| 236 | /* TODO: check if pcie clock is output/input - for bringup use input*/ |
| 237 | /* Enable PIN clock 100M_125M */ |
| 238 | mask = 0; |
| 239 | data = 0; |
| 240 | /* Only if clock is output, configure the clock-source mux */ |
| 241 | if (pcie_clk) { |
| 242 | mask |= HPIPE_MISC_CLK100M_125M_MASK; |
| 243 | data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; |
| 244 | } |
| 245 | /* |
| 246 | * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz |
| 247 | * clock |
| 248 | */ |
| 249 | mask |= HPIPE_MISC_TXDCLK_2X_MASK; |
| 250 | data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; |
| 251 | /* Enable 500MHz Clock */ |
| 252 | mask |= HPIPE_MISC_CLK500_EN_MASK; |
| 253 | data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; |
| 254 | if (pcie_clk) { /* output */ |
| 255 | /* Set reference clock comes from group 1 */ |
| 256 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
| 257 | data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 258 | } else { |
| 259 | /* Set reference clock comes from group 2 */ |
| 260 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
| 261 | data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; |
| 262 | } |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 263 | mask |= HPIPE_MISC_ICP_FORCE_MASK; |
| 264 | data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 265 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); |
| 266 | if (pcie_clk) { /* output */ |
| 267 | /* Set reference frequcency select - 0x2 for 25MHz*/ |
| 268 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 269 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 270 | } else { |
| 271 | /* Set reference frequcency select - 0x0 for 100MHz*/ |
| 272 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 273 | data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 274 | } |
| 275 | /* Set PHY mode to PCIe */ |
| 276 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 277 | data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 278 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 279 | |
| 280 | /* ref clock alignment */ |
| 281 | if (pcie_width != 1) { |
| 282 | mask = HPIPE_LANE_ALIGN_OFF_MASK; |
| 283 | data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; |
| 284 | reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); |
| 285 | } |
| 286 | |
| 287 | /* |
| 288 | * Set the amount of time spent in the LoZ state - set for 0x7 only if |
| 289 | * the PCIe clock is output |
| 290 | */ |
| 291 | if (pcie_clk) { |
| 292 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, |
| 293 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, |
| 294 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); |
| 295 | } |
| 296 | |
| 297 | /* Set Maximal PHY Generation Setting(8Gbps) */ |
| 298 | mask = HPIPE_INTERFACE_GEN_MAX_MASK; |
| 299 | data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 300 | /* Bypass frame detection and sync detection for RX DATA */ |
| 301 | mask = HPIPE_INTERFACE_DET_BYPASS_MASK; |
| 302 | data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 303 | /* Set Link Train Mode (Tx training control pins are used) */ |
| 304 | mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; |
| 305 | data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; |
| 306 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); |
| 307 | |
| 308 | /* Set Idle_sync enable */ |
| 309 | mask = HPIPE_PCIE_IDLE_SYNC_MASK; |
| 310 | data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; |
| 311 | /* Select bits for PCIE Gen3(32bit) */ |
| 312 | mask |= HPIPE_PCIE_SEL_BITS_MASK; |
| 313 | data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; |
| 314 | reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); |
| 315 | |
| 316 | /* Enable Tx_adapt_g1 */ |
| 317 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; |
| 318 | data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; |
| 319 | /* Enable Tx_adapt_gn1 */ |
| 320 | mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; |
| 321 | data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; |
| 322 | /* Disable Tx_adapt_g0 */ |
| 323 | mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; |
| 324 | data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; |
| 325 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); |
| 326 | |
| 327 | /* Set reg_tx_train_chk_init */ |
| 328 | mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; |
| 329 | data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; |
| 330 | /* Enable TX_COE_FM_PIN_PCIE3_EN */ |
| 331 | mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; |
| 332 | data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; |
| 333 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); |
| 334 | |
| 335 | debug("stage: TRx training parameters\n"); |
| 336 | /* Set Preset sweep configurations */ |
| 337 | mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; |
| 338 | data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; |
| 339 | |
| 340 | mask |= HPIPE_TX_NUM_OF_PRESET_MASK; |
| 341 | data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; |
| 342 | |
| 343 | mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; |
| 344 | data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; |
| 345 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); |
| 346 | |
| 347 | /* Tx train start configuration */ |
| 348 | mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; |
| 349 | data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; |
| 350 | |
| 351 | mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; |
| 352 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; |
| 353 | |
| 354 | mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; |
| 355 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; |
| 356 | |
| 357 | mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; |
| 358 | data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; |
| 359 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); |
| 360 | |
| 361 | /* Enable Tx train P2P */ |
| 362 | mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; |
| 363 | data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; |
| 364 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); |
| 365 | |
| 366 | /* Configure Tx train timeout */ |
| 367 | mask = HPIPE_TRX_TRAIN_TIMER_MASK; |
| 368 | data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; |
| 369 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); |
| 370 | |
| 371 | /* Disable G0/G1/GN1 adaptation */ |
| 372 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK |
| 373 | | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; |
| 374 | data = 0; |
| 375 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); |
| 376 | |
| 377 | /* Disable DTL frequency loop */ |
| 378 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; |
| 379 | data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; |
| 380 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); |
| 381 | |
| 382 | /* Configure G3 DFE */ |
| 383 | mask = HPIPE_G3_DFE_RES_MASK; |
| 384 | data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; |
| 385 | reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); |
| 386 | |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 387 | /* Use TX/RX training result for DFE */ |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 388 | mask = HPIPE_DFE_RES_FORCE_MASK; |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 389 | data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 390 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); |
| 391 | |
| 392 | /* Configure initial and final coefficient value for receiver */ |
Igal Liberman | c01f9fe | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 393 | mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; |
| 394 | data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 395 | |
Igal Liberman | c01f9fe | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 396 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; |
| 397 | data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 398 | |
Igal Liberman | c01f9fe | 2017-04-24 18:45:26 +0300 | [diff] [blame] | 399 | mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; |
| 400 | data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; |
| 401 | reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 402 | |
| 403 | /* Trigger sampler enable pulse */ |
| 404 | mask = HPIPE_SMAPLER_MASK; |
| 405 | data = 0x1 << HPIPE_SMAPLER_OFFSET; |
| 406 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); |
| 407 | udelay(5); |
| 408 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); |
| 409 | |
| 410 | /* FFE resistor tuning for different bandwidth */ |
| 411 | mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; |
| 412 | data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; |
| 413 | |
| 414 | mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 415 | data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 416 | reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); |
| 417 | |
Igal Liberman | ae07a70 | 2017-04-24 18:45:33 +0300 | [diff] [blame] | 418 | /* Pattern lock lost timeout disable */ |
| 419 | mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; |
| 420 | data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; |
| 421 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); |
| 422 | |
| 423 | /* Configure DFE adaptations */ |
| 424 | mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; |
| 425 | data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; |
| 426 | mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; |
| 427 | data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; |
| 428 | mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; |
| 429 | data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; |
| 430 | reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); |
| 431 | mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; |
| 432 | data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; |
| 433 | reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); |
| 434 | |
| 435 | /* Genration 2 setting 1*/ |
| 436 | mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; |
| 437 | data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; |
| 438 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; |
| 439 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; |
| 440 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; |
| 441 | data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; |
| 442 | reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); |
| 443 | |
| 444 | /* DFE enable */ |
| 445 | mask = HPIPE_G2_DFE_RES_MASK; |
| 446 | data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; |
| 447 | reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); |
| 448 | |
| 449 | /* Configure DFE Resolution */ |
| 450 | mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; |
| 451 | data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; |
| 452 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); |
| 453 | |
| 454 | /* VDD calibration control */ |
| 455 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; |
| 456 | data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; |
| 457 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); |
| 458 | |
| 459 | /* Set PLL Charge-pump Current Control */ |
| 460 | mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; |
| 461 | data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; |
| 462 | reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); |
| 463 | |
| 464 | /* Set lane rqualization remote setting */ |
| 465 | mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; |
| 466 | data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; |
| 467 | mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; |
| 468 | data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; |
| 469 | mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; |
| 470 | data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; |
| 471 | reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); |
| 472 | |
Stefan Roese | 7dda98e | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 473 | if (!is_end_point) { |
| 474 | /* Set phy in root complex mode */ |
| 475 | mask = HPIPE_CFG_PHY_RC_EP_MASK; |
| 476 | data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; |
| 477 | reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); |
| 478 | } |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 479 | |
| 480 | debug("stage: Comphy power up\n"); |
| 481 | |
| 482 | /* |
| 483 | * For PCIe by4 or by2 - release from reset only after finish to |
| 484 | * configure all lanes |
| 485 | */ |
| 486 | if ((pcie_width == 1) || (lane == (pcie_width - 1))) { |
| 487 | u32 i, start_lane, end_lane; |
| 488 | |
| 489 | if (pcie_width != 1) { |
| 490 | /* allows writing to all lanes in one write */ |
| 491 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 492 | 0x0 << |
| 493 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, |
| 494 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); |
| 495 | start_lane = 0; |
| 496 | end_lane = pcie_width; |
| 497 | |
| 498 | /* |
| 499 | * Release from PIPE soft reset |
| 500 | * for PCIe by4 or by2 - release from soft reset |
| 501 | * all lanes - can't use read modify write |
| 502 | */ |
| 503 | reg_set(HPIPE_ADDR(hpipe_base, 0) + |
| 504 | HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); |
| 505 | } else { |
| 506 | start_lane = lane; |
| 507 | end_lane = lane + 1; |
| 508 | |
| 509 | /* |
| 510 | * Release from PIPE soft reset |
| 511 | * for PCIe by4 or by2 - release from soft reset |
| 512 | * all lanes |
| 513 | */ |
| 514 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, |
| 515 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, |
| 516 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); |
| 517 | } |
| 518 | |
| 519 | |
| 520 | if (pcie_width != 1) { |
| 521 | /* disable writing to all lanes with one write */ |
| 522 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 523 | 0x3210 << |
| 524 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, |
| 525 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); |
| 526 | } |
| 527 | |
| 528 | debug("stage: Check PLL\n"); |
| 529 | /* Read lane status */ |
| 530 | for (i = start_lane; i < end_lane; i++) { |
| 531 | addr = HPIPE_ADDR(hpipe_base, i) + |
| 532 | HPIPE_LANE_STATUS1_REG; |
| 533 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; |
| 534 | mask = data; |
| 535 | data = polling_with_timeout(addr, data, mask, 15000); |
| 536 | if (data != 0) { |
| 537 | debug("Read from reg = %p - value = 0x%x\n", |
| 538 | hpipe_addr + HPIPE_LANE_STATUS1_REG, |
| 539 | data); |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 540 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 541 | ret = 0; |
| 542 | } |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | debug_exit(); |
| 547 | return ret; |
| 548 | } |
| 549 | |
| 550 | static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, |
| 551 | void __iomem *comphy_base) |
| 552 | { |
| 553 | u32 mask, data, ret = 1; |
| 554 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 555 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 556 | void __iomem *addr; |
| 557 | |
| 558 | debug_enter(); |
| 559 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 560 | /* RFU configurations - hard reset comphy */ |
| 561 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 562 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 563 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 564 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 565 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 566 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 567 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 568 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 569 | mask |= COMMON_PHY_PHY_MODE_MASK; |
| 570 | data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; |
| 571 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 572 | |
| 573 | /* release from hard reset */ |
| 574 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; |
| 575 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; |
| 576 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; |
| 577 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; |
| 578 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 579 | |
| 580 | /* Wait 1ms - until band gap and ref clock ready */ |
| 581 | mdelay(1); |
| 582 | |
| 583 | /* Start comphy Configuration */ |
| 584 | debug("stage: Comphy configuration\n"); |
| 585 | /* Set PIPE soft reset */ |
| 586 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; |
| 587 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; |
| 588 | /* Set PHY datapath width mode for V0 */ |
| 589 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; |
| 590 | data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; |
| 591 | /* Set Data bus width USB mode for V0 */ |
| 592 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; |
| 593 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; |
| 594 | /* Set CORE_CLK output frequency for 250Mhz */ |
| 595 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; |
| 596 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; |
| 597 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); |
| 598 | /* Set PLL ready delay for 0x2 */ |
| 599 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, |
| 600 | 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, |
| 601 | HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); |
| 602 | /* Set reference clock to come from group 1 - 25Mhz */ |
| 603 | reg_set(hpipe_addr + HPIPE_MISC_REG, |
| 604 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, |
| 605 | HPIPE_MISC_REFCLK_SEL_MASK); |
| 606 | /* Set reference frequcency select - 0x2 */ |
| 607 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 608 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 609 | /* Set PHY mode to USB - 0x5 */ |
| 610 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 611 | data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 612 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 613 | /* Set the amount of time spent in the LoZ state - set for 0x7 */ |
| 614 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, |
| 615 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, |
| 616 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); |
| 617 | /* Set max PHY generation setting - 5Gbps */ |
| 618 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, |
| 619 | 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, |
| 620 | HPIPE_INTERFACE_GEN_MAX_MASK); |
| 621 | /* Set select data width 20Bit (SEL_BITS[2:0]) */ |
| 622 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, |
| 623 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, |
| 624 | HPIPE_LOOPBACK_SEL_MASK); |
| 625 | /* select de-emphasize 3.5db */ |
| 626 | reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, |
| 627 | 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, |
| 628 | HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); |
| 629 | /* override tx margining from the MAC */ |
| 630 | reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, |
| 631 | 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, |
| 632 | HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); |
| 633 | |
| 634 | /* Start analog paramters from ETP(HW) */ |
| 635 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 636 | /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ |
| 637 | mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; |
| 638 | data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; |
| 639 | /* Set Override PHY DFE control pins for 0x1 */ |
| 640 | mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; |
| 641 | data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; |
| 642 | /* Set Spread Spectrum Clock Enable fot 0x1 */ |
| 643 | mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; |
| 644 | data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; |
| 645 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); |
| 646 | /* End of analog parameters */ |
| 647 | |
| 648 | debug("stage: Comphy power up\n"); |
| 649 | /* Release from PIPE soft reset */ |
| 650 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, |
| 651 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, |
| 652 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); |
| 653 | |
| 654 | /* wait 15ms - for comphy calibration done */ |
| 655 | debug("stage: Check PLL\n"); |
| 656 | /* Read lane status */ |
| 657 | addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; |
| 658 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; |
| 659 | mask = data; |
| 660 | data = polling_with_timeout(addr, data, mask, 15000); |
| 661 | if (data != 0) { |
| 662 | debug("Read from reg = %p - value = 0x%x\n", |
| 663 | hpipe_addr + HPIPE_LANE_STATUS1_REG, data); |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 664 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 665 | ret = 0; |
| 666 | } |
| 667 | |
| 668 | debug_exit(); |
| 669 | return ret; |
| 670 | } |
| 671 | |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 672 | static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, |
| 673 | u32 lane, u32 mode) |
| 674 | { |
| 675 | struct pt_regs pregs = {0}; |
| 676 | |
| 677 | pregs.regs[0] = function_id; |
| 678 | pregs.regs[1] = (unsigned long)comphy_base_addr; |
| 679 | pregs.regs[2] = lane; |
| 680 | pregs.regs[3] = mode; |
| 681 | |
| 682 | smc_call(&pregs); |
| 683 | |
| 684 | /* |
| 685 | * TODO: Firmware return 0 on success, temporary map it to u-boot |
| 686 | * convention, but after all comphy will be reworked the convention in |
| 687 | * u-boot should be change and this conversion removed |
| 688 | */ |
| 689 | return pregs.regs[0] ? 0 : 1; |
| 690 | } |
| 691 | |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 692 | static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 693 | void __iomem *comphy_base_addr, int cp_index, |
| 694 | u32 type) |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 695 | { |
| 696 | u32 mask, data, i, ret = 1; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 697 | void __iomem *sata_base = NULL; |
| 698 | int sata_node = -1; /* Set to -1 in order to read the first sata node */ |
| 699 | |
| 700 | debug_enter(); |
| 701 | |
| 702 | /* |
| 703 | * Assumption - each CP has only one SATA controller |
| 704 | * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 |
| 705 | * will return the first node always. |
| 706 | * In order to parse each CPs SATA node, fdt_node_offset_by_compatible |
| 707 | * must be called again (according to the CP id) |
| 708 | */ |
Igal Liberman | 528213d | 2017-04-24 18:45:32 +0300 | [diff] [blame] | 709 | for (i = 0; i < (cp_index + 1); i++) |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 710 | sata_node = fdt_node_offset_by_compatible( |
| 711 | gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); |
| 712 | |
| 713 | if (sata_node == 0) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 714 | pr_err("SATA node not found in FDT\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 719 | gd->fdt_blob, sata_node, "reg", 0, NULL, true); |
| 720 | if (sata_base == NULL) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 721 | pr_err("SATA address not found in FDT\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | debug("SATA address found in FDT %p\n", sata_base); |
| 726 | |
| 727 | debug("stage: MAC configuration - power down comphy\n"); |
| 728 | /* |
| 729 | * MAC configuration powe down comphy use indirect address for |
| 730 | * vendor spesific SATA control register |
| 731 | */ |
| 732 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 733 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 734 | SATA3_VENDOR_ADDR_MASK); |
| 735 | /* SATA 0 power down */ |
| 736 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 737 | data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 738 | /* SATA 1 power down */ |
| 739 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 740 | data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 741 | /* SATA SSU disable */ |
| 742 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 743 | data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 744 | /* SATA port 1 disable */ |
| 745 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 746 | data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 747 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 748 | |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 749 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 750 | |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 751 | /* |
| 752 | * MAC configuration power up comphy - power up PLL/TX/RX |
| 753 | * use indirect address for vendor spesific SATA control register |
| 754 | */ |
| 755 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 756 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 757 | SATA3_VENDOR_ADDR_MASK); |
| 758 | /* SATA 0 power up */ |
| 759 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 760 | data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 761 | /* SATA 1 power up */ |
| 762 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 763 | data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 764 | /* SATA SSU enable */ |
| 765 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 766 | data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 767 | /* SATA port 1 enable */ |
| 768 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 769 | data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 770 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 771 | |
| 772 | /* MBUS request size and interface select register */ |
| 773 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 774 | SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 775 | SATA3_VENDOR_ADDR_MASK); |
| 776 | /* Mbus regret enable */ |
| 777 | reg_set(sata_base + SATA3_VENDOR_DATA, |
| 778 | 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); |
| 779 | |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 780 | ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 781 | |
| 782 | debug_exit(); |
| 783 | return ret; |
| 784 | } |
| 785 | |
| 786 | static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, |
| 787 | void __iomem *comphy_base) |
| 788 | { |
| 789 | u32 mask, data, ret = 1; |
| 790 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); |
| 791 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); |
| 792 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); |
| 793 | void __iomem *addr; |
| 794 | |
| 795 | debug_enter(); |
| 796 | debug("stage: RFU configurations - hard reset comphy\n"); |
| 797 | /* RFU configurations - hard reset comphy */ |
| 798 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; |
| 799 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; |
| 800 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; |
| 801 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; |
| 802 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); |
| 803 | |
| 804 | if (lane == 2) { |
| 805 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 806 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, |
| 807 | COMMON_PHY_SD_CTRL1_RXAUI0_MASK); |
| 808 | } |
| 809 | if (lane == 4) { |
| 810 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, |
| 811 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, |
| 812 | COMMON_PHY_SD_CTRL1_RXAUI1_MASK); |
| 813 | } |
| 814 | |
| 815 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ |
| 816 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 817 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 818 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; |
| 819 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; |
| 820 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; |
| 821 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; |
| 822 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 823 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 824 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 825 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 826 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; |
| 827 | data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; |
| 828 | mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; |
| 829 | data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; |
| 830 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 831 | |
| 832 | /* release from hard reset */ |
| 833 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 834 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 835 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 836 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 837 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 838 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 839 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 840 | |
| 841 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; |
| 842 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; |
| 843 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; |
| 844 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; |
| 845 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 846 | |
| 847 | /* Wait 1ms - until band gap and ref clock ready */ |
| 848 | mdelay(1); |
| 849 | |
| 850 | /* Start comphy Configuration */ |
| 851 | debug("stage: Comphy configuration\n"); |
| 852 | /* set reference clock */ |
| 853 | reg_set(hpipe_addr + HPIPE_MISC_REG, |
| 854 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, |
| 855 | HPIPE_MISC_REFCLK_SEL_MASK); |
| 856 | /* Power and PLL Control */ |
| 857 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; |
| 858 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; |
| 859 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; |
| 860 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; |
| 861 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); |
| 862 | /* Loopback register */ |
| 863 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, |
| 864 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); |
| 865 | /* rx control 1 */ |
| 866 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; |
| 867 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; |
| 868 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; |
| 869 | data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; |
| 870 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); |
| 871 | /* DTL Control */ |
| 872 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, |
| 873 | 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, |
| 874 | HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); |
| 875 | |
| 876 | /* Set analog paramters from ETP(HW) */ |
| 877 | debug("stage: Analog paramters from ETP(HW)\n"); |
| 878 | /* SERDES External Configuration 2 */ |
| 879 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, |
| 880 | 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, |
| 881 | SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); |
| 882 | /* 0x7-DFE Resolution control */ |
| 883 | reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, |
| 884 | HPIPE_DFE_RES_FORCE_MASK); |
| 885 | /* 0xd-G1_Setting_0 */ |
| 886 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, |
| 887 | 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, |
| 888 | HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); |
| 889 | /* 0xE-G1_Setting_1 */ |
| 890 | mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; |
| 891 | data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; |
| 892 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; |
| 893 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; |
| 894 | mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; |
| 895 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; |
| 896 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |
| 897 | /* 0xA-DFE_Reg3 */ |
| 898 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; |
| 899 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; |
| 900 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; |
| 901 | data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; |
| 902 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); |
| 903 | |
| 904 | /* 0x111-G1_Setting_4 */ |
| 905 | mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; |
| 906 | data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; |
| 907 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); |
| 908 | |
| 909 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); |
| 910 | /* SERDES External Configuration */ |
| 911 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; |
| 912 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; |
| 913 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; |
| 914 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; |
| 915 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; |
| 916 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; |
| 917 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); |
| 918 | |
| 919 | |
| 920 | /* check PLL rx & tx ready */ |
| 921 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 922 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | |
| 923 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; |
| 924 | mask = data; |
| 925 | data = polling_with_timeout(addr, data, mask, 15000); |
| 926 | if (data != 0) { |
| 927 | debug("Read from reg = %p - value = 0x%x\n", |
| 928 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 929 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 930 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
| 931 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); |
| 932 | ret = 0; |
| 933 | } |
| 934 | |
| 935 | /* RX init */ |
| 936 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, |
| 937 | 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, |
| 938 | SD_EXTERNAL_CONFIG1_RX_INIT_MASK); |
| 939 | |
| 940 | /* check that RX init done */ |
| 941 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; |
| 942 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; |
| 943 | mask = data; |
| 944 | data = polling_with_timeout(addr, data, mask, 100); |
| 945 | if (data != 0) { |
| 946 | debug("Read from reg = %p - value = 0x%x\n", |
| 947 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 948 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 949 | ret = 0; |
| 950 | } |
| 951 | |
| 952 | debug("stage: RF Reset\n"); |
| 953 | /* RF Reset */ |
| 954 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; |
| 955 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; |
| 956 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; |
| 957 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; |
| 958 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); |
| 959 | |
| 960 | debug_exit(); |
| 961 | return ret; |
| 962 | } |
| 963 | |
| 964 | static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, |
| 965 | void __iomem *usb_cfg_addr, |
| 966 | void __iomem *utmi_cfg_addr, |
| 967 | u32 utmi_phy_port) |
| 968 | { |
| 969 | u32 mask, data; |
| 970 | |
| 971 | debug_enter(); |
| 972 | debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", |
| 973 | utmi_index); |
| 974 | /* Power down UTMI PHY */ |
| 975 | reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, |
| 976 | UTMI_PHY_CFG_PU_MASK); |
| 977 | |
| 978 | /* |
| 979 | * If UTMI connected to USB Device, configure mux prior to PHY init |
| 980 | * (Device can be connected to UTMI0 or to UTMI1) |
| 981 | */ |
Stefan Roese | e89acc4 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 982 | if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 983 | debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", |
| 984 | utmi_index); |
| 985 | /* USB3 Device UTMI enable */ |
| 986 | mask = UTMI_USB_CFG_DEVICE_EN_MASK; |
| 987 | data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; |
| 988 | /* USB3 Device UTMI MUX */ |
| 989 | mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; |
| 990 | data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; |
| 991 | reg_set(usb_cfg_addr, data, mask); |
| 992 | } |
| 993 | |
| 994 | /* Set Test suspendm mode */ |
| 995 | mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; |
| 996 | data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; |
| 997 | /* Enable Test UTMI select */ |
| 998 | mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; |
| 999 | data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; |
| 1000 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); |
| 1001 | |
| 1002 | /* Wait for UTMI power down */ |
| 1003 | mdelay(1); |
| 1004 | |
| 1005 | debug_exit(); |
| 1006 | return; |
| 1007 | } |
| 1008 | |
| 1009 | static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, |
| 1010 | void __iomem *usb_cfg_addr, |
| 1011 | void __iomem *utmi_cfg_addr, |
| 1012 | u32 utmi_phy_port) |
| 1013 | { |
| 1014 | u32 mask, data; |
| 1015 | |
| 1016 | debug_exit(); |
| 1017 | debug("stage: Configure UTMI PHY %d registers\n", utmi_index); |
| 1018 | /* Reference Clock Divider Select */ |
| 1019 | mask = UTMI_PLL_CTRL_REFDIV_MASK; |
| 1020 | data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; |
| 1021 | /* Feedback Clock Divider Select - 90 for 25Mhz*/ |
| 1022 | mask |= UTMI_PLL_CTRL_FBDIV_MASK; |
| 1023 | data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; |
| 1024 | /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ |
| 1025 | mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; |
| 1026 | data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; |
| 1027 | reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); |
| 1028 | |
| 1029 | /* Impedance Calibration Threshold Setting */ |
| 1030 | reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, |
| 1031 | 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, |
| 1032 | UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); |
| 1033 | |
| 1034 | /* Set LS TX driver strength coarse control */ |
| 1035 | mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; |
| 1036 | data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; |
| 1037 | /* Set LS TX driver fine adjustment */ |
| 1038 | mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; |
| 1039 | data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; |
| 1040 | reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); |
| 1041 | |
| 1042 | /* Enable SQ */ |
| 1043 | mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; |
| 1044 | data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; |
| 1045 | /* Enable analog squelch detect */ |
| 1046 | mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; |
| 1047 | data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; |
| 1048 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); |
| 1049 | |
| 1050 | /* Set External squelch calibration number */ |
| 1051 | mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; |
| 1052 | data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; |
| 1053 | /* Enable the External squelch calibration */ |
| 1054 | mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; |
| 1055 | data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; |
| 1056 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); |
| 1057 | |
| 1058 | /* Set Control VDAT Reference Voltage - 0.325V */ |
| 1059 | mask = UTMI_CHGDTC_CTRL_VDAT_MASK; |
| 1060 | data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; |
| 1061 | /* Set Control VSRC Reference Voltage - 0.6V */ |
| 1062 | mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; |
| 1063 | data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; |
| 1064 | reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); |
| 1065 | |
| 1066 | debug_exit(); |
| 1067 | return; |
| 1068 | } |
| 1069 | |
| 1070 | static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, |
| 1071 | void __iomem *usb_cfg_addr, |
| 1072 | void __iomem *utmi_cfg_addr, u32 utmi_phy_port) |
| 1073 | { |
| 1074 | u32 data, mask, ret = 1; |
| 1075 | void __iomem *addr; |
| 1076 | |
| 1077 | debug_enter(); |
| 1078 | debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", |
| 1079 | utmi_index); |
| 1080 | /* Power UP UTMI PHY */ |
| 1081 | reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, |
| 1082 | UTMI_PHY_CFG_PU_MASK); |
| 1083 | /* Disable Test UTMI select */ |
| 1084 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, |
| 1085 | 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, |
| 1086 | UTMI_CTRL_STATUS0_TEST_SEL_MASK); |
| 1087 | |
| 1088 | debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); |
| 1089 | addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; |
| 1090 | data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; |
| 1091 | mask = data; |
| 1092 | data = polling_with_timeout(addr, data, mask, 100); |
| 1093 | if (data != 0) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1094 | pr_err("Impedance calibration is not done\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1095 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1096 | ret = 0; |
| 1097 | } |
| 1098 | |
| 1099 | data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; |
| 1100 | mask = data; |
| 1101 | data = polling_with_timeout(addr, data, mask, 100); |
| 1102 | if (data != 0) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1103 | pr_err("PLL calibration is not done\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1104 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1105 | ret = 0; |
| 1106 | } |
| 1107 | |
| 1108 | addr = utmi_base_addr + UTMI_PLL_CTRL_REG; |
| 1109 | data = UTMI_PLL_CTRL_PLL_RDY_MASK; |
| 1110 | mask = data; |
| 1111 | data = polling_with_timeout(addr, data, mask, 100); |
| 1112 | if (data != 0) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1113 | pr_err("PLL is not ready\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1114 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 1115 | ret = 0; |
| 1116 | } |
| 1117 | |
| 1118 | if (ret) |
| 1119 | debug("Passed\n"); |
| 1120 | else |
| 1121 | debug("\n"); |
| 1122 | |
| 1123 | debug_exit(); |
| 1124 | return ret; |
| 1125 | } |
| 1126 | |
| 1127 | /* |
| 1128 | * comphy_utmi_phy_init initialize the UTMI PHY |
| 1129 | * the init split in 3 parts: |
| 1130 | * 1. Power down transceiver and PLL |
| 1131 | * 2. UTMI PHY configure |
| 1132 | * 3. Powe up transceiver and PLL |
| 1133 | * Note: - Power down/up should be once for both UTMI PHYs |
| 1134 | * - comphy_dedicated_phys_init call this function if at least there is |
| 1135 | * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is |
| 1136 | * legal |
| 1137 | */ |
| 1138 | static void comphy_utmi_phy_init(u32 utmi_phy_count, |
| 1139 | struct utmi_phy_data *cp110_utmi_data) |
| 1140 | { |
| 1141 | u32 i; |
| 1142 | |
| 1143 | debug_enter(); |
| 1144 | /* UTMI Power down */ |
| 1145 | for (i = 0; i < utmi_phy_count; i++) { |
| 1146 | comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, |
| 1147 | cp110_utmi_data[i].usb_cfg_addr, |
| 1148 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1149 | cp110_utmi_data[i].utmi_phy_port); |
| 1150 | } |
| 1151 | /* PLL Power down */ |
| 1152 | debug("stage: UTMI PHY power down PLL\n"); |
| 1153 | for (i = 0; i < utmi_phy_count; i++) { |
| 1154 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 1155 | 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 1156 | } |
| 1157 | /* UTMI configure */ |
| 1158 | for (i = 0; i < utmi_phy_count; i++) { |
| 1159 | comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, |
| 1160 | cp110_utmi_data[i].usb_cfg_addr, |
| 1161 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1162 | cp110_utmi_data[i].utmi_phy_port); |
| 1163 | } |
| 1164 | /* UTMI Power up */ |
| 1165 | for (i = 0; i < utmi_phy_count; i++) { |
| 1166 | if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, |
| 1167 | cp110_utmi_data[i].usb_cfg_addr, |
| 1168 | cp110_utmi_data[i].utmi_cfg_addr, |
| 1169 | cp110_utmi_data[i].utmi_phy_port)) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1170 | pr_err("Failed to initialize UTMI PHY %d\n", i); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1171 | continue; |
| 1172 | } |
| 1173 | printf("UTMI PHY %d initialized to ", i); |
Stefan Roese | e89acc4 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 1174 | if (cp110_utmi_data[i].utmi_phy_port == |
| 1175 | UTMI_PHY_TO_USB3_DEVICE0) |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1176 | printf("USB Device\n"); |
| 1177 | else |
| 1178 | printf("USB Host%d\n", |
| 1179 | cp110_utmi_data[i].utmi_phy_port); |
| 1180 | } |
| 1181 | /* PLL Power up */ |
| 1182 | debug("stage: UTMI PHY power up PLL\n"); |
| 1183 | for (i = 0; i < utmi_phy_count; i++) { |
| 1184 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 1185 | 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 1186 | } |
| 1187 | |
| 1188 | debug_exit(); |
| 1189 | return; |
| 1190 | } |
| 1191 | |
| 1192 | /* |
| 1193 | * comphy_dedicated_phys_init initialize the dedicated PHYs |
| 1194 | * - not muxed SerDes lanes e.g. UTMI PHY |
| 1195 | */ |
| 1196 | void comphy_dedicated_phys_init(void) |
| 1197 | { |
| 1198 | struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; |
| 1199 | int node; |
| 1200 | int i; |
| 1201 | |
| 1202 | debug_enter(); |
| 1203 | debug("Initialize USB UTMI PHYs\n"); |
| 1204 | |
| 1205 | /* Find the UTMI phy node in device tree and go over them */ |
| 1206 | node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, |
| 1207 | "marvell,mvebu-utmi-2.6.0"); |
| 1208 | |
| 1209 | i = 0; |
| 1210 | while (node > 0) { |
| 1211 | /* get base address of UTMI phy */ |
| 1212 | cp110_utmi_data[i].utmi_base_addr = |
| 1213 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1214 | gd->fdt_blob, node, "reg", 0, NULL, true); |
| 1215 | if (cp110_utmi_data[i].utmi_base_addr == NULL) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1216 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1217 | i++; |
| 1218 | continue; |
| 1219 | } |
| 1220 | |
| 1221 | /* get usb config address */ |
| 1222 | cp110_utmi_data[i].usb_cfg_addr = |
| 1223 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1224 | gd->fdt_blob, node, "reg", 1, NULL, true); |
| 1225 | if (cp110_utmi_data[i].usb_cfg_addr == NULL) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1226 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1227 | i++; |
| 1228 | continue; |
| 1229 | } |
| 1230 | |
| 1231 | /* get UTMI config address */ |
| 1232 | cp110_utmi_data[i].utmi_cfg_addr = |
| 1233 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 1234 | gd->fdt_blob, node, "reg", 2, NULL, true); |
| 1235 | if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1236 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1237 | i++; |
| 1238 | continue; |
| 1239 | } |
| 1240 | |
| 1241 | /* |
| 1242 | * get the port number (to check if the utmi connected to |
| 1243 | * host/device) |
| 1244 | */ |
| 1245 | cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( |
| 1246 | gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); |
| 1247 | if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1248 | pr_err("UTMI PHY port type is invalid\n"); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1249 | i++; |
| 1250 | continue; |
| 1251 | } |
| 1252 | |
| 1253 | node = fdt_node_offset_by_compatible( |
| 1254 | gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); |
| 1255 | i++; |
| 1256 | } |
| 1257 | |
| 1258 | if (i > 0) |
| 1259 | comphy_utmi_phy_init(i, cp110_utmi_data); |
| 1260 | |
| 1261 | debug_exit(); |
| 1262 | } |
| 1263 | |
| 1264 | static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 1265 | struct comphy_map *serdes_map) |
| 1266 | { |
| 1267 | void __iomem *comphy_base_addr; |
| 1268 | struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; |
| 1269 | struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; |
| 1270 | u32 lane, comphy_max_count; |
| 1271 | |
| 1272 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; |
| 1273 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; |
| 1274 | |
| 1275 | /* |
| 1276 | * Copy the SerDes map configuration for PIPE map and PHY map |
| 1277 | * the comphy_mux_init modify the type of the lane if the type |
| 1278 | * is not valid because we have 2 selectores run the |
| 1279 | * comphy_mux_init twice and after that update the original |
| 1280 | * serdes_map |
| 1281 | */ |
| 1282 | for (lane = 0; lane < comphy_max_count; lane++) { |
| 1283 | comphy_map_pipe_data[lane].type = serdes_map[lane].type; |
| 1284 | comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; |
| 1285 | comphy_map_phy_data[lane].type = serdes_map[lane].type; |
| 1286 | comphy_map_phy_data[lane].speed = serdes_map[lane].speed; |
| 1287 | } |
| 1288 | ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; |
| 1289 | comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, |
| 1290 | comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); |
| 1291 | |
| 1292 | ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; |
| 1293 | comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, |
| 1294 | comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); |
| 1295 | /* Fix the type after check the PHY and PIPE configuration */ |
| 1296 | for (lane = 0; lane < comphy_max_count; lane++) { |
| 1297 | if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && |
| 1298 | (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) |
| 1299 | serdes_map[lane].type = PHY_TYPE_UNCONNECTED; |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 1304 | struct comphy_map *serdes_map) |
| 1305 | { |
| 1306 | struct comphy_map *ptr_comphy_map; |
| 1307 | void __iomem *comphy_base_addr, *hpipe_base_addr; |
| 1308 | u32 comphy_max_count, lane, ret = 0; |
| 1309 | u32 pcie_width = 0; |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 1310 | u32 mode; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1311 | |
| 1312 | debug_enter(); |
| 1313 | |
| 1314 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; |
| 1315 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; |
| 1316 | hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; |
| 1317 | |
| 1318 | /* Config Comphy mux configuration */ |
| 1319 | comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); |
| 1320 | |
| 1321 | /* Check if the first 4 lanes configured as By-4 */ |
| 1322 | for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; |
| 1323 | lane++, ptr_comphy_map++) { |
| 1324 | if (ptr_comphy_map->type != PHY_TYPE_PEX0) |
| 1325 | break; |
| 1326 | pcie_width++; |
| 1327 | } |
| 1328 | |
| 1329 | for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; |
| 1330 | lane++, ptr_comphy_map++) { |
| 1331 | debug("Initialize serdes number %d\n", lane); |
| 1332 | debug("Serdes type = 0x%x\n", ptr_comphy_map->type); |
| 1333 | if (lane == 4) { |
| 1334 | /* |
| 1335 | * PCIe lanes above the first 4 lanes, can be only |
| 1336 | * by1 |
| 1337 | */ |
| 1338 | pcie_width = 1; |
| 1339 | } |
| 1340 | switch (ptr_comphy_map->type) { |
| 1341 | case PHY_TYPE_UNCONNECTED: |
Stefan Roese | 6ecc0b1 | 2017-04-24 18:45:24 +0300 | [diff] [blame] | 1342 | case PHY_TYPE_IGNORE: |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1343 | continue; |
| 1344 | break; |
| 1345 | case PHY_TYPE_PEX0: |
| 1346 | case PHY_TYPE_PEX1: |
| 1347 | case PHY_TYPE_PEX2: |
| 1348 | case PHY_TYPE_PEX3: |
| 1349 | ret = comphy_pcie_power_up( |
| 1350 | lane, pcie_width, ptr_comphy_map->clk_src, |
Stefan Roese | 7dda98e | 2017-04-24 18:45:22 +0300 | [diff] [blame] | 1351 | serdes_map->end_point, |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1352 | hpipe_base_addr, comphy_base_addr); |
| 1353 | break; |
| 1354 | case PHY_TYPE_SATA0: |
| 1355 | case PHY_TYPE_SATA1: |
| 1356 | case PHY_TYPE_SATA2: |
| 1357 | case PHY_TYPE_SATA3: |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 1358 | mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); |
| 1359 | ret = comphy_sata_power_up(lane, hpipe_base_addr, |
| 1360 | comphy_base_addr, |
| 1361 | ptr_chip_cfg->cp_index, |
| 1362 | mode); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1363 | break; |
| 1364 | case PHY_TYPE_USB3_HOST0: |
| 1365 | case PHY_TYPE_USB3_HOST1: |
| 1366 | case PHY_TYPE_USB3_DEVICE: |
| 1367 | ret = comphy_usb3_power_up(lane, hpipe_base_addr, |
| 1368 | comphy_base_addr); |
| 1369 | break; |
| 1370 | case PHY_TYPE_SGMII0: |
| 1371 | case PHY_TYPE_SGMII1: |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 1372 | if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { |
| 1373 | debug("Warning: "); |
| 1374 | debug("SGMII PHY speed in lane %d is invalid,", |
| 1375 | lane); |
| 1376 | debug(" set PHY speed to 1.25G\n"); |
| 1377 | ptr_comphy_map->speed = PHY_SPEED_1_25G; |
| 1378 | } |
| 1379 | |
| 1380 | /* |
| 1381 | * UINIT_ID not relevant for SGMII0 and SGMII1 - will be |
| 1382 | * ignored by firmware |
| 1383 | */ |
| 1384 | mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, |
| 1385 | COMPHY_UNIT_ID0, |
| 1386 | ptr_comphy_map->speed); |
| 1387 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 1388 | ptr_chip_cfg->comphy_base_addr, lane, |
| 1389 | mode); |
| 1390 | break; |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1391 | case PHY_TYPE_SGMII2: |
| 1392 | case PHY_TYPE_SGMII3: |
| 1393 | if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { |
| 1394 | debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", |
| 1395 | lane); |
| 1396 | ptr_comphy_map->speed = PHY_SPEED_1_25G; |
| 1397 | } |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 1398 | |
| 1399 | mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, |
| 1400 | COMPHY_UNIT_ID2, |
| 1401 | ptr_comphy_map->speed); |
| 1402 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 1403 | ptr_chip_cfg->comphy_base_addr, lane, |
| 1404 | mode); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1405 | break; |
Stefan Roese | cb68645 | 2017-04-24 18:45:21 +0300 | [diff] [blame] | 1406 | case PHY_TYPE_SFI: |
Grzegorz Jaszczyk | b24bb99 | 2020-10-18 17:11:11 +0300 | [diff] [blame^] | 1407 | mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, |
| 1408 | COMPHY_UNIT_ID0, |
| 1409 | ptr_comphy_map->speed); |
| 1410 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 1411 | ptr_chip_cfg->comphy_base_addr, lane, |
| 1412 | mode); |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1413 | break; |
| 1414 | case PHY_TYPE_RXAUI0: |
| 1415 | case PHY_TYPE_RXAUI1: |
| 1416 | ret = comphy_rxauii_power_up(lane, hpipe_base_addr, |
| 1417 | comphy_base_addr); |
| 1418 | break; |
| 1419 | default: |
| 1420 | debug("Unknown SerDes type, skip initialize SerDes %d\n", |
| 1421 | lane); |
| 1422 | break; |
| 1423 | } |
| 1424 | if (ret == 0) { |
| 1425 | /* |
Stefan Roese | d37f020 | 2017-04-24 18:45:25 +0300 | [diff] [blame] | 1426 | * If interface wans't initialized, set the lane to |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1427 | * PHY_TYPE_UNCONNECTED state. |
| 1428 | */ |
| 1429 | ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; |
Masahiro Yamada | 9b643e3 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 1430 | pr_err("PLL is not locked - Failed to initialize lane %d\n", |
Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 1431 | lane); |
| 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | debug_exit(); |
| 1436 | return 0; |
| 1437 | } |