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Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +02001/*
2 * exynos_lcd.h - Exynos LCD Controller structures
3 *
4 * (C) Copyright 2001
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _EXYNOS_LCD_H_
11#define _EXYNOS_LCD_H_
12
13enum {
14 FIMD_RGB_INTERFACE = 1,
15 FIMD_CPU_INTERFACE = 2,
16};
17
18enum exynos_fb_rgb_mode_t {
19 MODE_RGB_P = 0,
20 MODE_BGR_P = 1,
21 MODE_RGB_S = 2,
22 MODE_BGR_S = 3,
23};
24
25typedef struct vidinfo {
26 ushort vl_col; /* Number of columns (i.e. 640) */
27 ushort vl_row; /* Number of rows (i.e. 480) */
Hannes Petermaier604c7d42015-03-27 08:01:38 +010028 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020029 ushort vl_width; /* Width of display area in millimeters */
30 ushort vl_height; /* Height of display area in millimeters */
31
32 /* LCD configuration register */
33 u_char vl_freq; /* Frequency */
34 u_char vl_clkp; /* Clock polarity */
35 u_char vl_oep; /* Output Enable polarity */
36 u_char vl_hsp; /* Horizontal Sync polarity */
37 u_char vl_vsp; /* Vertical Sync polarity */
38 u_char vl_dp; /* Data polarity */
39 u_char vl_bpix; /* Bits per pixel */
40
41 /* Horizontal control register. Timing from data sheet */
42 u_char vl_hspw; /* Horz sync pulse width */
43 u_char vl_hfpd; /* Wait before of line */
44 u_char vl_hbpd; /* Wait end of line */
45
46 /* Vertical control register. */
47 u_char vl_vspw; /* Vertical sync pulse width */
48 u_char vl_vfpd; /* Wait before of frame */
49 u_char vl_vbpd; /* Wait end of frame */
50 u_char vl_cmd_allow_len; /* Wait end of frame */
51
52 unsigned int win_id;
53 unsigned int init_delay;
54 unsigned int power_on_delay;
55 unsigned int reset_delay;
56 unsigned int interface_mode;
57 unsigned int mipi_enabled;
58 unsigned int dp_enabled;
59 unsigned int cs_setup;
60 unsigned int wr_setup;
61 unsigned int wr_act;
62 unsigned int wr_hold;
63 unsigned int logo_on;
64 unsigned int logo_width;
65 unsigned int logo_height;
66 int logo_x_offset;
67 int logo_y_offset;
68 unsigned long logo_addr;
69 unsigned int rgb_mode;
70 unsigned int resolution;
71
72 /* parent clock name(MPLL, EPLL or VPLL) */
73 unsigned int pclk_name;
74 /* ratio value for source clock from parent clock. */
75 unsigned int sclk_div;
76
77 unsigned int dual_lcd_enabled;
Simon Glass8b449a62016-02-21 21:09:00 -070078 struct exynos_fb *reg;
Simon Glass652d15c2016-02-21 21:08:46 -070079 struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020080} vidinfo_t;
81
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020082#endif