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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk0f8c9762002-08-19 11:57:05 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
wdenk0f8c9762002-08-19 11:57:05 +000038
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenk0f8c9762002-08-19 11:57:05 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenk0f8c9762002-08-19 11:57:05 +000042
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_CPUCLOCK 66
44#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
wdenk0f8c9762002-08-19 11:57:05 +000045
wdenkc837dcb2004-01-20 23:12:12 +000046#define CONFIG_BAUDRATE 9600
wdenk0f8c9762002-08-19 11:57:05 +000047#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
49
wdenkc837dcb2004-01-20 23:12:12 +000050#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000051
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000054
55#undef CONFIG_WATCHDOG /* watchdog disabled */
56
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_PHY_ADDR 0 /* PHY address */
wdenk0f8c9762002-08-19 11:57:05 +000058
59#define CONFIG_IPADDR 10.0.18.222
60#define CONFIG_SERVERIP 10.0.18.190
61
Jon Loeliger11799432007-07-10 09:02:57 -050062
63/*
64 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
Jon Loeliger498ff9a2007-07-05 19:13:52 -050071/*
72 * Command line configuration.
73 */
74#include <config_cmd_default.h>
wdenk0f8c9762002-08-19 11:57:05 +000075
Jon Loeliger498ff9a2007-07-05 19:13:52 -050076#define CONFIG_CMD_DHCP
77#define CONFIG_CMD_IRQ
78#define CONFIG_CMD_ELF
79#define CONFIG_CMD_ASKENV
80
wdenk0f8c9762002-08-19 11:57:05 +000081
82/*
83 * Miscellaneous configurable options
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_LONGHELP /* undef to save memory */
86#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -050087#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000091#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk0f8c9762002-08-19 11:57:05 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
99#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000100
101/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000103 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000108
109#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
110
111/*-----------------------------------------------------------------------
112 * Definitions for initial stack pointer and data area (in DPRAM)
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
115#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
116#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
117#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
118#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000119
120/*-----------------------------------------------------------------------
121 * Start addresses for the final memory configuration
122 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_SDRAM_BASE 0x00000000
126#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
129#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000130
131/*
132 * For booting Linux, the board info and command line data
133 * have to be in the first 8 MB of memory, since this is
134 * the maximum mapped by the Linux kernel during initialization.
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000137/*-----------------------------------------------------------------------
138 * FLASH organization
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
141#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
144#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
147#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
148#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
wdenk0f8c9762002-08-19 11:57:05 +0000149/*
150 * The following defines are added for buggy IOP480 byte interface.
151 * All other boards should use the standard values (CPCI405 etc.)
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
154#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
155#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
wdenk0f8c9762002-08-19 11:57:05 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk0f8c9762002-08-19 11:57:05 +0000158
159#if 1 /* Use NVRAM for environment variables */
160/*-----------------------------------------------------------------------
161 * NVRAM organization
162 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200163#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */
165#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200166#define CONFIG_ENV_SIZE 0x0400 /* Size of Environment vars */
167#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
169#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
wdenk0f8c9762002-08-19 11:57:05 +0000170
171#else /* Use FLASH for environment variables */
172
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200173#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200174#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
175#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000176
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200177#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
wdenk0f8c9762002-08-19 11:57:05 +0000178
179#endif
180
181/*-----------------------------------------------------------------------
182 * PCI stuff
183 */
184#define CONFIG_PCI /* include pci support */
185#undef CONFIG_PCI_PNP
186
wdenkc837dcb2004-01-20 23:12:12 +0000187#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk0f8c9762002-08-19 11:57:05 +0000188
189#define CONFIG_TULIP
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_ETH_DEV_FN 0x0000
192#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
wdenk0f8c9762002-08-19 11:57:05 +0000193
wdenk0f8c9762002-08-19 11:57:05 +0000194/*
195 * Init Memory Controller:
196 *
197 * BR0/1 and OR0/1 (FLASH)
198 */
199
200#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
201#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */
202
203
204/*
205 * Internal Definitions
206 *
207 * Boot Flags
208 */
209#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
210#define BOOTFLAG_WARM 0x02 /* Software reboot */
211
212#endif /* __CONFIG_H */