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Michal Simek4f1ec4c2011-10-06 20:35:35 +00001/*
2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek4f1ec4c2011-10-06 20:35:35 +00007 */
8
9#include <config.h>
10#include <common.h>
Michal Simek75cc93f2015-12-08 15:44:41 +010011#include <dm.h>
Michal Simek4f1ec4c2011-10-06 20:35:35 +000012#include <net.h>
13#include <malloc.h>
14#include <asm/io.h>
15#include <phy.h>
16#include <miiphy.h>
Siva Durga Prasad Paladugud02a0b12017-01-06 16:18:50 +053017#include <wait_bit.h>
Michal Simek4f1ec4c2011-10-06 20:35:35 +000018
Michal Simek75cc93f2015-12-08 15:44:41 +010019DECLARE_GLOBAL_DATA_PTR;
20
Michal Simek4f1ec4c2011-10-06 20:35:35 +000021/* Link setup */
22#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
26
27/* Interrupt Status/Enable/Mask Registers bit definitions */
28#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
30
31/* Receive Configuration Word 1 (RCW1) Register bit definitions */
32#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
33
34/* Transmitter Configuration (TC) Register bit definitions */
35#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
36
37#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
38
39/* MDIO Management Configuration (MC) Register bit definitions */
40#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
41
42/* MDIO Management Control Register (MCR) Register bit definitions */
43#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
51
52#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
53
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +053054#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
55
Michal Simek4f1ec4c2011-10-06 20:35:35 +000056/* DMA macros */
57/* Bitmasks of XAXIDMA_CR_OFFSET register */
58#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
59#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
60
61/* Bitmasks of XAXIDMA_SR_OFFSET register */
62#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
63
64/* Bitmask for interrupts */
65#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
66#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
67#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
68
69/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
70#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
71#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
72
73#define DMAALIGN 128
74
75static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
76
77/* Reflect dma offsets */
78struct axidma_reg {
79 u32 control; /* DMACR */
80 u32 status; /* DMASR */
81 u32 current; /* CURDESC */
82 u32 reserved;
83 u32 tail; /* TAILDESC */
84};
85
86/* Private driver structures */
87struct axidma_priv {
88 struct axidma_reg *dmatx;
89 struct axidma_reg *dmarx;
90 int phyaddr;
Michal Simek6609f352015-12-09 14:39:42 +010091 struct axi_regs *iobase;
Michal Simek75cc93f2015-12-08 15:44:41 +010092 phy_interface_t interface;
Michal Simek4f1ec4c2011-10-06 20:35:35 +000093 struct phy_device *phydev;
94 struct mii_dev *bus;
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +053095 u8 eth_hasnobuf;
Michal Simek4f1ec4c2011-10-06 20:35:35 +000096};
97
98/* BD descriptors */
99struct axidma_bd {
100 u32 next; /* Next descriptor pointer */
101 u32 reserved1;
102 u32 phys; /* Buffer address */
103 u32 reserved2;
104 u32 reserved3;
105 u32 reserved4;
106 u32 cntrl; /* Control */
107 u32 status; /* Status */
108 u32 app0;
109 u32 app1; /* TX start << 16 | insert */
110 u32 app2; /* TX csum seed */
111 u32 app3;
112 u32 app4;
113 u32 sw_id_offset;
114 u32 reserved5;
115 u32 reserved6;
116};
117
118/* Static BDs - driver uses only one BD */
119static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
120static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
121
122struct axi_regs {
123 u32 reserved[3];
124 u32 is; /* 0xC: Interrupt status */
125 u32 reserved2;
126 u32 ie; /* 0x14: Interrupt enable */
127 u32 reserved3[251];
128 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
129 u32 tc; /* 0x408: Tx Configuration */
130 u32 reserved4;
131 u32 emmc; /* 0x410: EMAC mode configuration */
132 u32 reserved5[59];
133 u32 mdio_mc; /* 0x500: MII Management Config */
134 u32 mdio_mcr; /* 0x504: MII Management Control */
135 u32 mdio_mwd; /* 0x508: MII Management Write Data */
136 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
137 u32 reserved6[124];
138 u32 uaw0; /* 0x700: Unicast address word 0 */
139 u32 uaw1; /* 0x704: Unicast address word 1 */
140};
141
142/* Use MII register 1 (MII status register) to detect PHY */
143#define PHY_DETECT_REG 1
144
145/*
146 * Mask used to verify certain PHY features (or register contents)
147 * in the register above:
148 * 0x1000: 10Mbps full duplex support
149 * 0x0800: 10Mbps half duplex support
150 * 0x0008: Auto-negotiation support
151 */
152#define PHY_DETECT_MASK 0x1808
153
Michal Simekf36bbcc2015-12-09 14:36:31 +0100154static inline int mdio_wait(struct axi_regs *regs)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000155{
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000156 u32 timeout = 200;
157
158 /* Wait till MDIO interface is ready to accept a new transaction. */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530159 while (timeout && (!(readl(&regs->mdio_mcr)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000160 & XAE_MDIO_MCR_READY_MASK))) {
161 timeout--;
162 udelay(1);
163 }
164 if (!timeout) {
165 printf("%s: Timeout\n", __func__);
166 return 1;
167 }
168 return 0;
169}
170
Michal Simek0d78abf2015-12-09 14:44:38 +0100171static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
172 u16 *val)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000173{
Michal Simek0d78abf2015-12-09 14:44:38 +0100174 struct axi_regs *regs = priv->iobase;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000175 u32 mdioctrlreg = 0;
176
Michal Simekf36bbcc2015-12-09 14:36:31 +0100177 if (mdio_wait(regs))
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000178 return 1;
179
180 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
181 XAE_MDIO_MCR_PHYAD_MASK) |
182 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
183 & XAE_MDIO_MCR_REGAD_MASK) |
184 XAE_MDIO_MCR_INITIATE_MASK |
185 XAE_MDIO_MCR_OP_READ_MASK;
186
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530187 writel(mdioctrlreg, &regs->mdio_mcr);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000188
Michal Simekf36bbcc2015-12-09 14:36:31 +0100189 if (mdio_wait(regs))
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000190 return 1;
191
192 /* Read data */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530193 *val = readl(&regs->mdio_mrd);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000194 return 0;
195}
196
Michal Simek0d78abf2015-12-09 14:44:38 +0100197static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
198 u32 data)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000199{
Michal Simek0d78abf2015-12-09 14:44:38 +0100200 struct axi_regs *regs = priv->iobase;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000201 u32 mdioctrlreg = 0;
202
Michal Simekf36bbcc2015-12-09 14:36:31 +0100203 if (mdio_wait(regs))
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000204 return 1;
205
206 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
207 XAE_MDIO_MCR_PHYAD_MASK) |
208 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
209 & XAE_MDIO_MCR_REGAD_MASK) |
210 XAE_MDIO_MCR_INITIATE_MASK |
211 XAE_MDIO_MCR_OP_WRITE_MASK;
212
213 /* Write data */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530214 writel(data, &regs->mdio_mwd);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000215
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530216 writel(mdioctrlreg, &regs->mdio_mcr);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000217
Michal Simekf36bbcc2015-12-09 14:36:31 +0100218 if (mdio_wait(regs))
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000219 return 1;
220
221 return 0;
222}
223
Michal Simek5d0449d2015-12-08 16:10:05 +0100224static int axiemac_phy_init(struct udevice *dev)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000225{
226 u16 phyreg;
Michal Simek5d0449d2015-12-08 16:10:05 +0100227 u32 i, ret;
Michal Simek75cc93f2015-12-08 15:44:41 +0100228 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6609f352015-12-09 14:39:42 +0100229 struct axi_regs *regs = priv->iobase;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000230 struct phy_device *phydev;
231
232 u32 supported = SUPPORTED_10baseT_Half |
233 SUPPORTED_10baseT_Full |
234 SUPPORTED_100baseT_Half |
235 SUPPORTED_100baseT_Full |
236 SUPPORTED_1000baseT_Half |
237 SUPPORTED_1000baseT_Full;
238
Michal Simek5d0449d2015-12-08 16:10:05 +0100239 /* Set default MDIO divisor */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530240 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
Michal Simek5d0449d2015-12-08 16:10:05 +0100241
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000242 if (priv->phyaddr == -1) {
243 /* Detect the PHY address */
244 for (i = 31; i >= 0; i--) {
Michal Simek0d78abf2015-12-09 14:44:38 +0100245 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000246 if (!ret && (phyreg != 0xFFFF) &&
247 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
248 /* Found a valid PHY address */
249 priv->phyaddr = i;
250 debug("axiemac: Found valid phy address, %x\n",
Michal Simek2652a622015-12-09 10:54:53 +0100251 i);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000252 break;
253 }
254 }
255 }
256
257 /* Interface - look at tsec */
Siva Durga Prasad Paladugu9c0da762016-02-21 15:46:14 +0530258 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000259
260 phydev->supported &= supported;
261 phydev->advertising = phydev->supported;
262 priv->phydev = phydev;
263 phy_config(phydev);
Michal Simek5d0449d2015-12-08 16:10:05 +0100264
265 return 0;
266}
267
268/* Setting axi emac and phy to proper setting */
269static int setup_phy(struct udevice *dev)
270{
Siva Durga Prasad Paladugu8964f242016-02-21 15:46:15 +0530271 u16 temp;
272 u32 speed, emmc_reg, ret;
Michal Simek5d0449d2015-12-08 16:10:05 +0100273 struct axidma_priv *priv = dev_get_priv(dev);
274 struct axi_regs *regs = priv->iobase;
275 struct phy_device *phydev = priv->phydev;
276
Siva Durga Prasad Paladugu8964f242016-02-21 15:46:15 +0530277 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
278 /*
279 * In SGMII cases the isolate bit might set
280 * after DMA and ethernet resets and hence
281 * check and clear if set.
282 */
283 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
284 if (ret)
285 return 0;
286 if (temp & BMCR_ISOLATE) {
287 temp &= ~BMCR_ISOLATE;
288 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
289 if (ret)
290 return 0;
291 }
292 }
293
Timur Tabi11af8d62012-07-09 08:52:43 +0000294 if (phy_startup(phydev)) {
295 printf("axiemac: could not initialize PHY %s\n",
296 phydev->dev->name);
297 return 0;
298 }
Michal Simek6f9b9372013-11-21 16:15:51 +0100299 if (!phydev->link) {
300 printf("%s: No link.\n", phydev->dev->name);
301 return 0;
302 }
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000303
304 switch (phydev->speed) {
305 case 1000:
306 speed = XAE_EMMC_LINKSPD_1000;
307 break;
308 case 100:
309 speed = XAE_EMMC_LINKSPD_100;
310 break;
311 case 10:
312 speed = XAE_EMMC_LINKSPD_10;
313 break;
314 default:
315 return 0;
316 }
317
318 /* Setup the emac for the phy speed */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530319 emmc_reg = readl(&regs->emmc);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000320 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
321 emmc_reg |= speed;
322
323 /* Write new speed setting out to Axi Ethernet */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530324 writel(emmc_reg, &regs->emmc);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000325
326 /*
327 * Setting the operating speed of the MAC needs a delay. There
328 * doesn't seem to be register to poll, so please consider this
329 * during your application design.
330 */
331 udelay(1);
332
333 return 1;
334}
335
336/* STOP DMA transfers */
Michal Simekad499e42015-12-16 09:18:12 +0100337static void axiemac_stop(struct udevice *dev)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000338{
Michal Simek75cc93f2015-12-08 15:44:41 +0100339 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000340 u32 temp;
341
342 /* Stop the hardware */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530343 temp = readl(&priv->dmatx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000344 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530345 writel(temp, &priv->dmatx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000346
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530347 temp = readl(&priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000348 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530349 writel(temp, &priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000350
351 debug("axiemac: Halted\n");
352}
353
Michal Simekf0985482015-12-09 14:53:51 +0100354static int axi_ethernet_init(struct axidma_priv *priv)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000355{
Michal Simekf0985482015-12-09 14:53:51 +0100356 struct axi_regs *regs = priv->iobase;
Siva Durga Prasad Paladugud02a0b12017-01-06 16:18:50 +0530357 int err;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000358
359 /*
360 * Check the status of the MgtRdy bit in the interrupt status
361 * registers. This must be done to allow the MGT clock to become stable
362 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
363 * will be valid until this bit is valid.
364 * The bit is always a 1 for all other PHY interfaces.
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530365 * Interrupt status and enable registers are not available in non
366 * processor mode and hence bypass in this mode
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000367 */
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530368 if (!priv->eth_hasnobuf) {
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100369 err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK,
370 true, 200, false);
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530371 if (err) {
372 printf("%s: Timeout\n", __func__);
373 return 1;
374 }
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000375
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530376 /*
377 * Stop the device and reset HW
378 * Disable interrupts
379 */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530380 writel(0, &regs->ie);
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530381 }
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000382
383 /* Disable the receiver */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530384 writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000385
386 /*
387 * Stopping the receiver in mid-packet causes a dropped packet
388 * indication from HW. Clear it.
389 */
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530390 if (!priv->eth_hasnobuf) {
391 /* Set the interrupt status register to clear the interrupt */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530392 writel(XAE_INT_RXRJECT_MASK, &regs->is);
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530393 }
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000394
395 /* Setup HW */
396 /* Set default MDIO divisor */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530397 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000398
399 debug("axiemac: InitHw done\n");
400 return 0;
401}
402
Michal Simekad499e42015-12-16 09:18:12 +0100403static int axiemac_write_hwaddr(struct udevice *dev)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000404{
Michal Simek75cc93f2015-12-08 15:44:41 +0100405 struct eth_pdata *pdata = dev_get_platdata(dev);
406 struct axidma_priv *priv = dev_get_priv(dev);
407 struct axi_regs *regs = priv->iobase;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000408
409 /* Set the MAC address */
Michal Simek75cc93f2015-12-08 15:44:41 +0100410 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
411 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530412 writel(val, &regs->uaw0);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000413
Michal Simek75cc93f2015-12-08 15:44:41 +0100414 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530415 val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
416 writel(val, &regs->uaw1);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000417 return 0;
418}
419
420/* Reset DMA engine */
Michal Simekf0985482015-12-09 14:53:51 +0100421static void axi_dma_init(struct axidma_priv *priv)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000422{
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000423 u32 timeout = 500;
424
425 /* Reset the engine so the hardware starts from a known state */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530426 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
427 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000428
429 /* At the initialization time, hardware should finish reset quickly */
430 while (timeout--) {
431 /* Check transmit/receive channel */
432 /* Reset is done when the reset bit is low */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530433 if (!((readl(&priv->dmatx->control) |
434 readl(&priv->dmarx->control))
Michal Simek3e3f8ba2015-10-28 11:00:47 +0100435 & XAXIDMA_CR_RESET_MASK)) {
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000436 break;
437 }
438 }
439 if (!timeout)
440 printf("%s: Timeout\n", __func__);
441}
442
Michal Simekad499e42015-12-16 09:18:12 +0100443static int axiemac_start(struct udevice *dev)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000444{
Michal Simek75cc93f2015-12-08 15:44:41 +0100445 struct axidma_priv *priv = dev_get_priv(dev);
446 struct axi_regs *regs = priv->iobase;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000447 u32 temp;
448
449 debug("axiemac: Init started\n");
450 /*
451 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
452 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
453 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
454 * would ensure a reset of AxiEthernet.
455 */
Michal Simekf0985482015-12-09 14:53:51 +0100456 axi_dma_init(priv);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000457
458 /* Initialize AxiEthernet hardware. */
Michal Simekf0985482015-12-09 14:53:51 +0100459 if (axi_ethernet_init(priv))
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000460 return -1;
461
462 /* Disable all RX interrupts before RxBD space setup */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530463 temp = readl(&priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000464 temp &= ~XAXIDMA_IRQ_ALL_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530465 writel(temp, &priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000466
467 /* Start DMA RX channel. Now it's ready to receive data.*/
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530468 writel((u32)&rx_bd, &priv->dmarx->current);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000469
470 /* Setup the BD. */
471 memset(&rx_bd, 0, sizeof(rx_bd));
472 rx_bd.next = (u32)&rx_bd;
473 rx_bd.phys = (u32)&rxframe;
474 rx_bd.cntrl = sizeof(rxframe);
475 /* Flush the last BD so DMA core could see the updates */
476 flush_cache((u32)&rx_bd, sizeof(rx_bd));
477
478 /* It is necessary to flush rxframe because if you don't do it
479 * then cache can contain uninitialized data */
480 flush_cache((u32)&rxframe, sizeof(rxframe));
481
482 /* Start the hardware */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530483 temp = readl(&priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000484 temp |= XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530485 writel(temp, &priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000486
487 /* Rx BD is ready - start */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530488 writel((u32)&rx_bd, &priv->dmarx->tail);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000489
490 /* Enable TX */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530491 writel(XAE_TC_TX_MASK, &regs->tc);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000492 /* Enable RX */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530493 writel(XAE_RCW1_RX_MASK, &regs->rcw1);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000494
495 /* PHY setup */
496 if (!setup_phy(dev)) {
Michal Simekad499e42015-12-16 09:18:12 +0100497 axiemac_stop(dev);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000498 return -1;
499 }
500
501 debug("axiemac: Init complete\n");
502 return 0;
503}
504
Michal Simek75cc93f2015-12-08 15:44:41 +0100505static int axiemac_send(struct udevice *dev, void *ptr, int len)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000506{
Michal Simek75cc93f2015-12-08 15:44:41 +0100507 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000508 u32 timeout;
509
510 if (len > PKTSIZE_ALIGN)
511 len = PKTSIZE_ALIGN;
512
513 /* Flush packet to main memory to be trasfered by DMA */
514 flush_cache((u32)ptr, len);
515
516 /* Setup Tx BD */
517 memset(&tx_bd, 0, sizeof(tx_bd));
518 /* At the end of the ring, link the last BD back to the top */
519 tx_bd.next = (u32)&tx_bd;
520 tx_bd.phys = (u32)ptr;
521 /* Save len */
522 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
523 XAXIDMA_BD_CTRL_TXEOF_MASK;
524
525 /* Flush the last BD so DMA core could see the updates */
526 flush_cache((u32)&tx_bd, sizeof(tx_bd));
527
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530528 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000529 u32 temp;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530530 writel((u32)&tx_bd, &priv->dmatx->current);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000531 /* Start the hardware */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530532 temp = readl(&priv->dmatx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000533 temp |= XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530534 writel(temp, &priv->dmatx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000535 }
536
537 /* Start transfer */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530538 writel((u32)&tx_bd, &priv->dmatx->tail);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000539
540 /* Wait for transmission to complete */
541 debug("axiemac: Waiting for tx to be done\n");
542 timeout = 200;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530543 while (timeout && (!(readl(&priv->dmatx->status) &
Michal Simek3e3f8ba2015-10-28 11:00:47 +0100544 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000545 timeout--;
546 udelay(1);
547 }
548 if (!timeout) {
549 printf("%s: Timeout\n", __func__);
550 return 1;
551 }
552
553 debug("axiemac: Sending complete\n");
554 return 0;
555}
556
Michal Simekf0985482015-12-09 14:53:51 +0100557static int isrxready(struct axidma_priv *priv)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000558{
559 u32 status;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000560
561 /* Read pending interrupts */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530562 status = readl(&priv->dmarx->status);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000563
564 /* Acknowledge pending interrupts */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530565 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000566
567 /*
568 * If Reception done interrupt is asserted, call RX call back function
569 * to handle the processed BDs and then raise the according flag.
570 */
571 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
572 return 1;
573
574 return 0;
575}
576
Michal Simek75cc93f2015-12-08 15:44:41 +0100577static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000578{
579 u32 length;
Michal Simek75cc93f2015-12-08 15:44:41 +0100580 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000581 u32 temp;
582
583 /* Wait for an incoming packet */
Michal Simekf0985482015-12-09 14:53:51 +0100584 if (!isrxready(priv))
Michal Simek75cc93f2015-12-08 15:44:41 +0100585 return -1;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000586
587 debug("axiemac: RX data ready\n");
588
589 /* Disable IRQ for a moment till packet is handled */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530590 temp = readl(&priv->dmarx->control);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000591 temp &= ~XAXIDMA_IRQ_ALL_MASK;
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530592 writel(temp, &priv->dmarx->control);
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530593 if (!priv->eth_hasnobuf)
594 length = rx_bd.app4 & 0xFFFF; /* max length mask */
595 else
596 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000597
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000598#ifdef DEBUG
599 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
600#endif
Michal Simek97d23632015-12-09 14:13:23 +0100601
602 *packetp = rxframe;
603 return length;
604}
605
606static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
607{
608 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000609
610#ifdef DEBUG
611 /* It is useful to clear buffer to be sure that it is consistent */
612 memset(rxframe, 0, sizeof(rxframe));
613#endif
614 /* Setup RxBD */
615 /* Clear the whole buffer and setup it again - all flags are cleared */
616 memset(&rx_bd, 0, sizeof(rx_bd));
617 rx_bd.next = (u32)&rx_bd;
618 rx_bd.phys = (u32)&rxframe;
619 rx_bd.cntrl = sizeof(rxframe);
620
621 /* Write bd to HW */
622 flush_cache((u32)&rx_bd, sizeof(rx_bd));
623
624 /* It is necessary to flush rxframe because if you don't do it
625 * then cache will contain previous packet */
626 flush_cache((u32)&rxframe, sizeof(rxframe));
627
628 /* Rx BD is ready - start again */
Siva Durga Prasad Paladugua04a5da2017-11-23 12:23:12 +0530629 writel((u32)&rx_bd, &priv->dmarx->tail);
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000630
631 debug("axiemac: RX completed, framelength = %d\n", length);
632
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000633 return 0;
634}
635
Michal Simek75cc93f2015-12-08 15:44:41 +0100636static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
637 int devad, int reg)
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000638{
Michal Simek75cc93f2015-12-08 15:44:41 +0100639 int ret;
640 u16 value;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000641
Michal Simek75cc93f2015-12-08 15:44:41 +0100642 ret = phyread(bus->priv, addr, reg, &value);
643 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
644 value, ret);
645 return value;
Michal Simek4f1ec4c2011-10-06 20:35:35 +0000646}
Michal Simek75cc93f2015-12-08 15:44:41 +0100647
648static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
649 int reg, u16 value)
650{
651 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
652 return phywrite(bus->priv, addr, reg, value);
653}
654
655static int axi_emac_probe(struct udevice *dev)
656{
657 struct axidma_priv *priv = dev_get_priv(dev);
658 int ret;
659
660 priv->bus = mdio_alloc();
661 priv->bus->read = axiemac_miiphy_read;
662 priv->bus->write = axiemac_miiphy_write;
663 priv->bus->priv = priv;
Michal Simek75cc93f2015-12-08 15:44:41 +0100664
Michal Simek6516e3f2016-12-08 10:25:44 +0100665 ret = mdio_register_seq(priv->bus, dev->seq);
Michal Simek75cc93f2015-12-08 15:44:41 +0100666 if (ret)
667 return ret;
668
Michal Simek5d0449d2015-12-08 16:10:05 +0100669 axiemac_phy_init(dev);
670
Michal Simek75cc93f2015-12-08 15:44:41 +0100671 return 0;
672}
673
674static int axi_emac_remove(struct udevice *dev)
675{
676 struct axidma_priv *priv = dev_get_priv(dev);
677
678 free(priv->phydev);
679 mdio_unregister(priv->bus);
680 mdio_free(priv->bus);
681
682 return 0;
683}
684
685static const struct eth_ops axi_emac_ops = {
Michal Simekad499e42015-12-16 09:18:12 +0100686 .start = axiemac_start,
Michal Simek75cc93f2015-12-08 15:44:41 +0100687 .send = axiemac_send,
688 .recv = axiemac_recv,
Michal Simek97d23632015-12-09 14:13:23 +0100689 .free_pkt = axiemac_free_pkt,
Michal Simekad499e42015-12-16 09:18:12 +0100690 .stop = axiemac_stop,
691 .write_hwaddr = axiemac_write_hwaddr,
Michal Simek75cc93f2015-12-08 15:44:41 +0100692};
693
694static int axi_emac_ofdata_to_platdata(struct udevice *dev)
695{
696 struct eth_pdata *pdata = dev_get_platdata(dev);
697 struct axidma_priv *priv = dev_get_priv(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -0700698 int node = dev_of_offset(dev);
Michal Simek75cc93f2015-12-08 15:44:41 +0100699 int offset = 0;
700 const char *phy_mode;
701
Simon Glassa821c4a2017-05-17 17:18:05 -0600702 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Michal Simek75cc93f2015-12-08 15:44:41 +0100703 priv->iobase = (struct axi_regs *)pdata->iobase;
704
Simon Glasse160f7d2017-01-17 16:52:55 -0700705 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
Michal Simek75cc93f2015-12-08 15:44:41 +0100706 "axistream-connected");
707 if (offset <= 0) {
708 printf("%s: axistream is not found\n", __func__);
709 return -EINVAL;
710 }
Siva Durga Prasad Paladugudc1fcc42017-06-22 11:14:55 +0530711 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
712 offset, "reg");
Michal Simek75cc93f2015-12-08 15:44:41 +0100713 if (!priv->dmatx) {
714 printf("%s: axi_dma register space not found\n", __func__);
715 return -EINVAL;
716 }
717 /* RX channel offset is 0x30 */
718 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
719
720 priv->phyaddr = -1;
721
Simon Glasse160f7d2017-01-17 16:52:55 -0700722 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
Michal Simek75cc93f2015-12-08 15:44:41 +0100723 if (offset > 0)
724 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
725
Simon Glasse160f7d2017-01-17 16:52:55 -0700726 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Michal Simek75cc93f2015-12-08 15:44:41 +0100727 if (phy_mode)
728 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
729 if (pdata->phy_interface == -1) {
Michal Simekceb04e12016-02-08 13:54:05 +0100730 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
Michal Simek75cc93f2015-12-08 15:44:41 +0100731 return -EINVAL;
732 }
733 priv->interface = pdata->phy_interface;
734
Siva Durga Prasad Paladugu89ce5a92017-01-06 16:27:15 +0530735 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
736 "xlnx,eth-hasnobuf");
737
Michal Simek75cc93f2015-12-08 15:44:41 +0100738 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
739 priv->phyaddr, phy_string_for_interface(priv->interface));
740
741 return 0;
742}
743
744static const struct udevice_id axi_emac_ids[] = {
745 { .compatible = "xlnx,axi-ethernet-1.00.a" },
746 { }
747};
748
749U_BOOT_DRIVER(axi_emac) = {
750 .name = "axi_emac",
751 .id = UCLASS_ETH,
752 .of_match = axi_emac_ids,
753 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
754 .probe = axi_emac_probe,
755 .remove = axi_emac_remove,
756 .ops = &axi_emac_ops,
757 .priv_auto_alloc_size = sizeof(struct axidma_priv),
758 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
759};