blob: cad458ac7107e41773fb9658e7661c7bbd7226d7 [file] [log] [blame]
Mario Six3bf65cb2018-09-27 09:19:34 +02001config GDSYS_LEGACY_OSD_CMDS
2 bool
3 help
4 Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
5 gdsys devices.
6
Mario Sixb335fb62019-03-29 10:18:08 +01007config SYS_FPGA0_BASE
8 hex
9 default E0600000
10 help
11 The base address of the first FPGA's register map.
12
13config SYS_FPGA0_SIZE
14 hex
15 default 1
16 help
17 The base address of the first FPGA's register map.
18
19config SYS_FPGA1_BASE
20 hex
21 help
22 The base address of the second FPGA's register map.
23
24config SYS_FPGA1_SIZE
25 hex
26 help
27 The base address of the second FPGA's register map.
28
Dirk Eibach50dcf892014-11-13 19:21:18 +010029if TARGET_HRCON
30
31config SYS_BOARD
32 default "mpc8308"
33
34config SYS_VENDOR
35 default "gdsys"
36
37config SYS_CONFIG_NAME
38 default "hrcon"
39
Mario Six3bf65cb2018-09-27 09:19:34 +020040config GDSYS_LEGACY_OSD_CMDS
41 default y
42
Dirk Eibach50dcf892014-11-13 19:21:18 +010043endif
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +010044
45if TARGET_STRIDER
46
47config SYS_BOARD
48 default "mpc8308"
49
50config SYS_VENDOR
51 default "gdsys"
52
53config SYS_CONFIG_NAME
54 default "strider"
55
Mario Six3bf65cb2018-09-27 09:19:34 +020056config GDSYS_LEGACY_OSD_CMDS
57 default y
Dirk Eibacha3f9d6c2015-10-28 11:46:32 +010058endif
Simon Glass070f3162017-05-17 03:25:35 -060059
60config CMD_IOLOOP
61 bool "Enable 'ioloop' and 'ioreflect' commands"
62 help
63 These commands provide FPGA tests.