blob: 6adf7e7b74b6246d0db368c93546da0407a4cd71 [file] [log] [blame]
Dave Liu24c3aca2006-12-07 21:13:15 +08001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <common.h>
16#include <ioports.h>
17#include <mpc83xx.h>
18#include <i2c.h>
19#include <spd.h>
20#include <miiphy.h>
21#include <command.h>
22#if defined(CONFIG_PCI)
23#include <pci.h>
24#endif
25#if defined(CONFIG_SPD_EEPROM)
26#include <spd_sdram.h>
27#else
28#include <asm/mmu.h>
29#endif
Kim Phillipsb3458d22007-12-20 15:57:28 -060030#if defined(CONFIG_OF_LIBFDT)
Kim Phillips3fde9e82007-08-15 22:30:33 -050031#include <libfdt.h>
Dave Liu24c3aca2006-12-07 21:13:15 +080032#endif
Tony Li14778582007-08-17 10:35:59 +080033#if defined(CONFIG_PQ_MDS_PIB)
Kim Phillipse58fe952007-08-16 22:53:09 -050034#include "../common/pq-mds-pib.h"
Tony Li14778582007-08-17 10:35:59 +080035#endif
Dave Liu24c3aca2006-12-07 21:13:15 +080036
37const qe_iop_conf_t qe_iop_conf_tab[] = {
38 /* ETH3 */
39 {1, 0, 1, 0, 1}, /* TxD0 */
40 {1, 1, 1, 0, 1}, /* TxD1 */
41 {1, 2, 1, 0, 1}, /* TxD2 */
42 {1, 3, 1, 0, 1}, /* TxD3 */
43 {1, 9, 1, 0, 1}, /* TxER */
44 {1, 12, 1, 0, 1}, /* TxEN */
45 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
46
47 {1, 4, 2, 0, 1}, /* RxD0 */
48 {1, 5, 2, 0, 1}, /* RxD1 */
49 {1, 6, 2, 0, 1}, /* RxD2 */
50 {1, 7, 2, 0, 1}, /* RxD3 */
51 {1, 8, 2, 0, 1}, /* RxER */
52 {1, 10, 2, 0, 1}, /* RxDV */
53 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
54 {1, 11, 2, 0, 1}, /* COL */
55 {1, 13, 2, 0, 1}, /* CRS */
56
57 /* ETH4 */
58 {1, 18, 1, 0, 1}, /* TxD0 */
59 {1, 19, 1, 0, 1}, /* TxD1 */
60 {1, 20, 1, 0, 1}, /* TxD2 */
61 {1, 21, 1, 0, 1}, /* TxD3 */
62 {1, 27, 1, 0, 1}, /* TxER */
63 {1, 30, 1, 0, 1}, /* TxEN */
64 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
65
66 {1, 22, 2, 0, 1}, /* RxD0 */
67 {1, 23, 2, 0, 1}, /* RxD1 */
68 {1, 24, 2, 0, 1}, /* RxD2 */
69 {1, 25, 2, 0, 1}, /* RxD3 */
70 {1, 26, 1, 0, 1}, /* RxER */
71 {1, 28, 2, 0, 1}, /* Rx_DV */
72 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
73 {1, 29, 2, 0, 1}, /* COL */
74 {1, 31, 2, 0, 1}, /* CRS */
75
76 {3, 4, 3, 0, 2}, /* MDIO */
77 {3, 5, 1, 0, 2}, /* MDC */
78
79 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
80};
81
82int board_early_init_f(void)
83{
84 volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
85
86 /* Enable flash write */
87 bcsr[9] &= ~0x08;
88
89 return 0;
90}
91
Tony Li14778582007-08-17 10:35:59 +080092int board_early_init_r(void)
93{
94#ifdef CONFIG_PQ_MDS_PIB
95 pib_init();
96#endif
97 return 0;
98}
99
Dave Liu24c3aca2006-12-07 21:13:15 +0800100int fixed_sdram(void);
101
102long int initdram(int board_type)
103{
104 volatile immap_t *im = (immap_t *) CFG_IMMR;
105 u32 msize = 0;
106
107 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
108 return -1;
109
110 /* DDR SDRAM - Main SODIMM */
111 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
112
113 msize = fixed_sdram();
114
Dave Liu24c3aca2006-12-07 21:13:15 +0800115 /* return total bus SDRAM size(bytes) -- DDR */
116 return (msize * 1024 * 1024);
117}
118
119/*************************************************************************
120 * fixed sdram init -- doesn't use serial presence detect.
121 ************************************************************************/
122int fixed_sdram(void)
123{
124 volatile immap_t *im = (immap_t *) CFG_IMMR;
125 u32 msize = 0;
126 u32 ddr_size;
127 u32 ddr_size_log2;
128
129 msize = CFG_DDR_SIZE;
130 for (ddr_size = msize << 20, ddr_size_log2 = 0;
131 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
132 if (ddr_size & 1) {
133 return -1;
134 }
135 }
136 im->sysconf.ddrlaw[0].ar =
137 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
138#if (CFG_DDR_SIZE != 128)
139#warning Currenly any ddr size other than 128 is not supported
140#endif
141 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
142 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
143 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
144 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
145 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
146 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
147 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
148 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
149 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
150 im->ddr.sdram_mode = CFG_DDR_MODE;
151 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
152 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
153 __asm__ __volatile__ ("sync");
154 udelay(200);
155
156 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
157 __asm__ __volatile__ ("sync");
158 return msize;
159}
160
161int checkboard(void)
162{
163 puts("Board: Freescale MPC832XEMDS\n");
164 return 0;
165}
166
Kim Phillips3fde9e82007-08-15 22:30:33 -0500167#if defined(CONFIG_OF_BOARD_SETUP)
168void ft_board_setup(void *blob, bd_t *bd)
Dave Liu24c3aca2006-12-07 21:13:15 +0800169{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500170 ft_cpu_setup(blob, bd);
171#ifdef CONFIG_PCI
172 ft_pci_setup(blob, bd);
173#endif
Dave Liu24c3aca2006-12-07 21:13:15 +0800174}
175#endif