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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roesea4884832014-10-22 12:13:19 +02002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Stefan Roesea4884832014-10-22 12:13:19 +02004 */
5
6#ifndef _CONFIG_DB_MV7846MP_GP_H
7#define _CONFIG_DB_MV7846MP_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roesea4884832014-10-22 12:13:19 +020012
Stefan Roese2923c2d2015-08-06 14:27:36 +020013/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roesea4884832014-10-22 12:13:19 +020018#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
21 * Commands configuration
22 */
Stefan Roesea4884832014-10-22 12:13:19 +020023
24/* I2C */
25#define CONFIG_SYS_I2C
26#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020027#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesea4884832014-10-22 12:13:19 +020028#define CONFIG_SYS_I2C_SLAVE 0x0
29#define CONFIG_SYS_I2C_SPEED 100000
30
31/* SPI NOR flash default params, used by sf commands */
32#define CONFIG_SF_DEFAULT_SPEED 1000000
33#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roesea4884832014-10-22 12:13:19 +020034
35/* Environment in SPI NOR flash */
Stefan Roesea4884832014-10-22 12:13:19 +020036#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
37#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
38#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
39
Stefan Roesea4884832014-10-22 12:13:19 +020040#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roesea4884832014-10-22 12:13:19 +020041
Stefan Roesea4884832014-10-22 12:13:19 +020042/*
43 * mv-common.h should be defined after CMD configs since it used them
44 * to enable certain macros
45 */
46#include "mv-common.h"
47
Stefan Roesee7778ec2015-01-19 11:33:47 +010048/*
49 * Memory layout while starting into the bin_hdr via the
50 * BootROM:
51 *
52 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
53 * 0x4000.4030 bin_hdr start address
54 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
55 * 0x4007.fffc BootROM stack top
56 *
57 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
58 * L2 cache thus cannot be used.
59 */
60
61/* SPL */
62/* Defines for SPL */
Stefan Roesee7778ec2015-01-19 11:33:47 +010063#define CONFIG_SPL_TEXT_BASE 0x40004030
64#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
65
66#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
67#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
68
Stefan Roese64512232015-11-25 07:37:00 +010069#ifdef CONFIG_SPL_BUILD
70#define CONFIG_SYS_MALLOC_SIMPLE
71#endif
Stefan Roesee7778ec2015-01-19 11:33:47 +010072
73#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
74#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
75
Stefan Roesee7778ec2015-01-19 11:33:47 +010076/* SPL related SPI defines */
Stefan Roesee7778ec2015-01-19 11:33:47 +010077#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
78
79/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roesee7778ec2015-01-19 11:33:47 +010080#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
Stefan Roese698ffab2015-12-10 15:02:38 +010081#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roesee7778ec2015-01-19 11:33:47 +010082
Stefan Roesea4884832014-10-22 12:13:19 +020083#endif /* _CONFIG_DB_MV7846MP_GP_H */