Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 3 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 4 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 5 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com |
| 6 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
| 7 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 8 | * |
| 9 | * (C) Copyright 2007 |
| 10 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | /* define DEBUG for debugging output (obviously ;-)) */ |
| 29 | #if 0 |
| 30 | #define DEBUG |
| 31 | #endif |
| 32 | |
| 33 | #include <common.h> |
| 34 | #include <asm/processor.h> |
| 35 | #include <asm/mmu.h> |
| 36 | #include <asm/io.h> |
| 37 | #include <ppc440.h> |
| 38 | |
| 39 | #include "sdram.h" |
| 40 | |
| 41 | /* |
| 42 | * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory |
| 43 | * region. Right now the cache should still be disabled in U-Boot because of the |
| 44 | * EMAC driver, that need it's buffer descriptor to be located in non cached |
| 45 | * memory. |
| 46 | * |
| 47 | * If at some time this restriction doesn't apply anymore, just define |
| 48 | * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup |
| 49 | * everything correctly. |
| 50 | */ |
| 51 | #ifdef CFG_ENABLE_SDRAM_CACHE |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 52 | #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 53 | #else |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 54 | #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 55 | #endif |
| 56 | |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 57 | void dcbz_area(u32 start_address, u32 num_bytes); |
| 58 | void dflush(void); |
| 59 | |
| 60 | #ifdef CONFIG_ADD_RAM_INFO |
| 61 | static u32 is_ecc_enabled(void) |
| 62 | { |
| 63 | u32 val; |
| 64 | |
| 65 | mfsdram(DDR0_22, val); |
| 66 | val &= DDR0_22_CTRL_RAW_MASK; |
| 67 | if (val) |
| 68 | return 1; |
| 69 | else |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | void board_add_ram_info(int use_default) |
| 74 | { |
| 75 | PPC440_SYS_INFO board_cfg; |
| 76 | u32 val; |
| 77 | |
| 78 | if (is_ecc_enabled()) |
| 79 | puts(" (ECC"); |
| 80 | else |
| 81 | puts(" (ECC not"); |
| 82 | |
| 83 | get_sys_info(&board_cfg); |
| 84 | printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000); |
| 85 | |
| 86 | mfsdram(DDR0_03, val); |
| 87 | val = DDR0_03_CASLAT_DECODE(val); |
| 88 | printf(", CL%d)", val); |
| 89 | } |
| 90 | #endif |
| 91 | |
| 92 | static int wait_for_dlllock(void) |
| 93 | { |
| 94 | u32 val; |
| 95 | int wait = 0; |
| 96 | |
| 97 | /* |
| 98 | * Wait for the DCC master delay line to finish calibration |
| 99 | */ |
| 100 | mtdcr(ddrcfga, DDR0_17); |
| 101 | val = DDR0_17_DLLLOCKREG_UNLOCKED; |
| 102 | |
| 103 | while (wait != 0xffff) { |
| 104 | val = mfdcr(ddrcfgd); |
| 105 | if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) |
| 106 | /* dlllockreg bit on */ |
| 107 | return 0; |
| 108 | else |
| 109 | wait++; |
| 110 | } |
| 111 | debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); |
| 112 | debug("Waiting for dlllockreg bit to raise\n"); |
| 113 | |
| 114 | return -1; |
| 115 | } |
| 116 | |
| 117 | #if defined(CONFIG_DDR_DATA_EYE) |
| 118 | int wait_for_dram_init_complete(void) |
| 119 | { |
| 120 | u32 val; |
| 121 | int wait = 0; |
| 122 | |
| 123 | /* |
| 124 | * Wait for 'DRAM initialization complete' bit in status register |
| 125 | */ |
| 126 | mtdcr(ddrcfga, DDR0_00); |
| 127 | |
| 128 | while (wait != 0xffff) { |
| 129 | val = mfdcr(ddrcfgd); |
| 130 | if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) |
| 131 | /* 'DRAM initialization complete' bit */ |
| 132 | return 0; |
| 133 | else |
| 134 | wait++; |
| 135 | } |
| 136 | |
| 137 | debug("DRAM initialization complete bit in status register did not rise\n"); |
| 138 | |
| 139 | return -1; |
| 140 | } |
| 141 | |
| 142 | #define NUM_TRIES 64 |
| 143 | #define NUM_READS 10 |
| 144 | |
| 145 | void denali_core_search_data_eye(u32 start_addr, u32 memory_size) |
| 146 | { |
| 147 | int k, j; |
| 148 | u32 val; |
| 149 | u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; |
| 150 | u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; |
| 151 | u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; |
| 152 | u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; |
| 153 | volatile u32 *ram_pointer; |
| 154 | u32 test[NUM_TRIES] = { |
| 155 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
| 156 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
| 157 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
| 158 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
| 159 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
| 160 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
| 161 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
| 162 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
| 163 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
| 164 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
| 165 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
| 166 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
| 167 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
| 168 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
| 169 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, |
| 170 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; |
| 171 | |
| 172 | ram_pointer = (volatile u32 *)start_addr; |
| 173 | |
| 174 | for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { |
| 175 | /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ |
| 176 | |
| 177 | /* |
| 178 | * De-assert 'start' parameter. |
| 179 | */ |
| 180 | mtdcr(ddrcfga, DDR0_02); |
| 181 | val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; |
| 182 | mtdcr(ddrcfgd, val); |
| 183 | |
| 184 | /* |
| 185 | * Set 'wr_dqs_shift' |
| 186 | */ |
| 187 | mtdcr(ddrcfga, DDR0_09); |
| 188 | val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) |
| 189 | | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); |
| 190 | mtdcr(ddrcfgd, val); |
| 191 | |
| 192 | /* |
| 193 | * Set 'dqs_out_shift' = wr_dqs_shift + 32 |
| 194 | */ |
| 195 | dqs_out_shift = wr_dqs_shift + 32; |
| 196 | mtdcr(ddrcfga, DDR0_22); |
| 197 | val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) |
| 198 | | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); |
| 199 | mtdcr(ddrcfgd, val); |
| 200 | |
| 201 | passing_cases = 0; |
| 202 | |
| 203 | for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { |
| 204 | /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ |
| 205 | /* |
| 206 | * Set 'dll_dqs_delay_X'. |
| 207 | */ |
| 208 | /* dll_dqs_delay_0 */ |
| 209 | mtdcr(ddrcfga, DDR0_17); |
| 210 | val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) |
| 211 | | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); |
| 212 | mtdcr(ddrcfgd, val); |
| 213 | /* dll_dqs_delay_1 to dll_dqs_delay_4 */ |
| 214 | mtdcr(ddrcfga, DDR0_18); |
| 215 | val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) |
| 216 | | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) |
| 217 | | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) |
| 218 | | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) |
| 219 | | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); |
| 220 | mtdcr(ddrcfgd, val); |
| 221 | /* dll_dqs_delay_5 to dll_dqs_delay_8 */ |
| 222 | mtdcr(ddrcfga, DDR0_19); |
| 223 | val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) |
| 224 | | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) |
| 225 | | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) |
| 226 | | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) |
| 227 | | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); |
| 228 | mtdcr(ddrcfgd, val); |
| 229 | |
| 230 | ppcMsync(); |
| 231 | ppcMbar(); |
| 232 | |
| 233 | /* |
| 234 | * Assert 'start' parameter. |
| 235 | */ |
| 236 | mtdcr(ddrcfga, DDR0_02); |
| 237 | val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; |
| 238 | mtdcr(ddrcfgd, val); |
| 239 | |
| 240 | ppcMsync(); |
| 241 | ppcMbar(); |
| 242 | |
| 243 | /* |
| 244 | * Wait for the DCC master delay line to finish calibration |
| 245 | */ |
| 246 | if (wait_for_dlllock() != 0) { |
| 247 | printf("dlllock did not occur !!!\n"); |
| 248 | printf("denali_core_search_data_eye!!!\n"); |
| 249 | printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", |
| 250 | wr_dqs_shift, dll_dqs_delay_X); |
| 251 | hang(); |
| 252 | } |
| 253 | ppcMsync(); |
| 254 | ppcMbar(); |
| 255 | |
| 256 | if (wait_for_dram_init_complete() != 0) { |
| 257 | printf("dram init complete did not occur !!!\n"); |
| 258 | printf("denali_core_search_data_eye!!!\n"); |
| 259 | printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", |
| 260 | wr_dqs_shift, dll_dqs_delay_X); |
| 261 | hang(); |
| 262 | } |
| 263 | udelay(100); /* wait 100us to ensure init is really completed !!! */ |
| 264 | |
| 265 | /* write values */ |
| 266 | for (j=0; j<NUM_TRIES; j++) { |
| 267 | ram_pointer[j] = test[j]; |
| 268 | |
| 269 | /* clear any cache at ram location */ |
| 270 | __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); |
| 271 | } |
| 272 | |
| 273 | /* read values back */ |
| 274 | for (j=0; j<NUM_TRIES; j++) { |
| 275 | for (k=0; k<NUM_READS; k++) { |
| 276 | /* clear any cache at ram location */ |
| 277 | __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); |
| 278 | |
| 279 | if (ram_pointer[j] != test[j]) |
| 280 | break; |
| 281 | } |
| 282 | |
| 283 | /* read error */ |
| 284 | if (k != NUM_READS) |
| 285 | break; |
| 286 | } |
| 287 | |
| 288 | /* See if the dll_dqs_delay_X value passed.*/ |
| 289 | if (j < NUM_TRIES) { |
| 290 | /* Failed */ |
| 291 | passing_cases = 0; |
| 292 | /* break; */ |
| 293 | } else { |
| 294 | /* Passed */ |
| 295 | if (passing_cases == 0) |
| 296 | dll_dqs_delay_X_sw_val = dll_dqs_delay_X; |
| 297 | passing_cases++; |
| 298 | if (passing_cases >= max_passing_cases) { |
| 299 | max_passing_cases = passing_cases; |
| 300 | wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; |
| 301 | dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; |
| 302 | dll_dqs_delay_X_end_window = dll_dqs_delay_X; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | /* |
| 307 | * De-assert 'start' parameter. |
| 308 | */ |
| 309 | mtdcr(ddrcfga, DDR0_02); |
| 310 | val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; |
| 311 | mtdcr(ddrcfgd, val); |
| 312 | |
| 313 | } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ |
| 314 | |
| 315 | } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ |
| 316 | |
| 317 | /* |
| 318 | * Largest passing window is now detected. |
| 319 | */ |
| 320 | |
| 321 | /* Compute dll_dqs_delay_X value */ |
| 322 | dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; |
| 323 | wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; |
| 324 | |
| 325 | debug("DQS calibration - Window detected:\n"); |
| 326 | debug("max_passing_cases = %d\n", max_passing_cases); |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 327 | debug("wr_dqs_shift = %d\n", wr_dqs_shift); |
| 328 | debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 329 | debug("dll_dqs_delay_X window = %d - %d\n", |
| 330 | dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); |
| 331 | |
| 332 | /* |
| 333 | * De-assert 'start' parameter. |
| 334 | */ |
| 335 | mtdcr(ddrcfga, DDR0_02); |
| 336 | val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; |
| 337 | mtdcr(ddrcfgd, val); |
| 338 | |
| 339 | /* |
| 340 | * Set 'wr_dqs_shift' |
| 341 | */ |
| 342 | mtdcr(ddrcfga, DDR0_09); |
| 343 | val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) |
| 344 | | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); |
| 345 | mtdcr(ddrcfgd, val); |
| 346 | debug("DDR0_09=0x%08lx\n", val); |
| 347 | |
| 348 | /* |
| 349 | * Set 'dqs_out_shift' = wr_dqs_shift + 32 |
| 350 | */ |
| 351 | dqs_out_shift = wr_dqs_shift + 32; |
| 352 | mtdcr(ddrcfga, DDR0_22); |
| 353 | val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) |
| 354 | | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); |
| 355 | mtdcr(ddrcfgd, val); |
| 356 | debug("DDR0_22=0x%08lx\n", val); |
| 357 | |
| 358 | /* |
| 359 | * Set 'dll_dqs_delay_X'. |
| 360 | */ |
| 361 | /* dll_dqs_delay_0 */ |
| 362 | mtdcr(ddrcfga, DDR0_17); |
| 363 | val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) |
| 364 | | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); |
| 365 | mtdcr(ddrcfgd, val); |
| 366 | debug("DDR0_17=0x%08lx\n", val); |
| 367 | |
| 368 | /* dll_dqs_delay_1 to dll_dqs_delay_4 */ |
| 369 | mtdcr(ddrcfga, DDR0_18); |
| 370 | val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) |
| 371 | | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) |
| 372 | | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) |
| 373 | | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) |
| 374 | | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); |
| 375 | mtdcr(ddrcfgd, val); |
| 376 | debug("DDR0_18=0x%08lx\n", val); |
| 377 | |
| 378 | /* dll_dqs_delay_5 to dll_dqs_delay_8 */ |
| 379 | mtdcr(ddrcfga, DDR0_19); |
| 380 | val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) |
| 381 | | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) |
| 382 | | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) |
| 383 | | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) |
| 384 | | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); |
| 385 | mtdcr(ddrcfgd, val); |
| 386 | debug("DDR0_19=0x%08lx\n", val); |
| 387 | |
| 388 | /* |
| 389 | * Assert 'start' parameter. |
| 390 | */ |
| 391 | mtdcr(ddrcfga, DDR0_02); |
| 392 | val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; |
| 393 | mtdcr(ddrcfgd, val); |
| 394 | |
| 395 | ppcMsync(); |
| 396 | ppcMbar(); |
| 397 | |
| 398 | /* |
| 399 | * Wait for the DCC master delay line to finish calibration |
| 400 | */ |
| 401 | if (wait_for_dlllock() != 0) { |
| 402 | printf("dlllock did not occur !!!\n"); |
| 403 | hang(); |
| 404 | } |
| 405 | ppcMsync(); |
| 406 | ppcMbar(); |
| 407 | |
| 408 | if (wait_for_dram_init_complete() != 0) { |
| 409 | printf("dram init complete did not occur !!!\n"); |
| 410 | hang(); |
| 411 | } |
| 412 | udelay(100); /* wait 100us to ensure init is really completed !!! */ |
| 413 | } |
| 414 | #endif /* CONFIG_DDR_DATA_EYE */ |
| 415 | |
| 416 | #ifdef CONFIG_DDR_ECC |
| 417 | static void wait_ddr_idle(void) |
| 418 | { |
| 419 | /* |
| 420 | * Controller idle status cannot be determined for Denali |
| 421 | * DDR2 code. Just return here. |
| 422 | */ |
| 423 | } |
| 424 | |
| 425 | static void blank_string(int size) |
| 426 | { |
| 427 | int i; |
| 428 | |
| 429 | for (i=0; i<size; i++) |
| 430 | putc('\b'); |
| 431 | for (i=0; i<size; i++) |
| 432 | putc(' '); |
| 433 | for (i=0; i<size; i++) |
| 434 | putc('\b'); |
| 435 | } |
| 436 | |
| 437 | static void program_ecc(u32 start_address, |
| 438 | u32 num_bytes, |
| 439 | u32 tlb_word2_i_value) |
| 440 | { |
| 441 | u32 current_address; |
| 442 | u32 end_address; |
| 443 | u32 address_increment; |
| 444 | u32 val; |
| 445 | char str[] = "ECC generation -"; |
| 446 | char slash[] = "\\|/-\\|/-"; |
| 447 | int loop = 0; |
| 448 | int loopi = 0; |
| 449 | |
| 450 | current_address = start_address; |
| 451 | |
| 452 | sync(); |
| 453 | eieio(); |
| 454 | wait_ddr_idle(); |
| 455 | |
| 456 | if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { |
| 457 | /* ECC bit set method for non-cached memory */ |
| 458 | address_increment = 4; |
| 459 | end_address = current_address + num_bytes; |
| 460 | |
| 461 | puts(str); |
| 462 | |
| 463 | while (current_address < end_address) { |
| 464 | *((u32 *)current_address) = 0x00000000; |
| 465 | current_address += address_increment; |
| 466 | |
| 467 | if ((loop++ % (2 << 20)) == 0) { |
| 468 | putc('\b'); |
| 469 | putc(slash[loopi++ % 8]); |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | blank_string(strlen(str)); |
| 474 | } else { |
| 475 | /* ECC bit set method for cached memory */ |
Stefan Roese | ea9f6bc | 2007-07-31 08:37:01 +0200 | [diff] [blame] | 476 | #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 477 | /* |
| 478 | * Some boards (like lwmon5) need to preserve the memory |
| 479 | * content upon ECC generation (for the log-buffer). |
| 480 | * Therefore we don't fill the memory with a pattern or |
| 481 | * just zero it, but write the same values back that are |
| 482 | * already in the memory cells. |
| 483 | */ |
| 484 | address_increment = CFG_CACHELINE_SIZE; |
| 485 | end_address = current_address + num_bytes; |
| 486 | |
| 487 | current_address = start_address; |
| 488 | while (current_address < end_address) { |
Stefan Roese | ea9f6bc | 2007-07-31 08:37:01 +0200 | [diff] [blame] | 489 | /* |
| 490 | * TODO: Th following sequence doesn't work correctly. |
| 491 | * Just invalidating and flushing the cache doesn't |
| 492 | * seem to trigger the re-write of the memory. |
| 493 | */ |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 494 | ppcDcbi(current_address); |
| 495 | ppcDcbf(current_address); |
| 496 | current_address += CFG_CACHELINE_SIZE; |
| 497 | } |
| 498 | #else |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 499 | dcbz_area(start_address, num_bytes); |
| 500 | dflush(); |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 501 | #endif |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | sync(); |
| 505 | eieio(); |
| 506 | wait_ddr_idle(); |
| 507 | |
| 508 | /* Clear error status */ |
| 509 | mfsdram(DDR0_00, val); |
| 510 | mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); |
| 511 | |
| 512 | /* Set 'int_mask' parameter to functionnal value */ |
| 513 | mfsdram(DDR0_01, val); |
| 514 | mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); |
| 515 | |
| 516 | sync(); |
| 517 | eieio(); |
| 518 | wait_ddr_idle(); |
| 519 | } |
| 520 | #endif |
| 521 | |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 522 | /************************************************************************* |
| 523 | * |
| 524 | * initdram -- 440EPx's DDR controller is a DENALI Core |
| 525 | * |
| 526 | ************************************************************************/ |
| 527 | long int initdram (int board_type) |
| 528 | { |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 529 | #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ |
| 530 | /* CL=3 */ |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 531 | mtsdram(DDR0_02, 0x00000000); |
| 532 | |
| 533 | mtsdram(DDR0_00, 0x0000190A); |
| 534 | mtsdram(DDR0_01, 0x01000000); |
| 535 | mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */ |
| 536 | |
| 537 | mtsdram(DDR0_04, 0x0A030300); |
| 538 | mtsdram(DDR0_05, 0x02020308); |
| 539 | mtsdram(DDR0_06, 0x0103C812); |
| 540 | mtsdram(DDR0_07, 0x00090100); |
| 541 | mtsdram(DDR0_08, 0x02c80001); |
| 542 | mtsdram(DDR0_09, 0x00011D5F); |
| 543 | mtsdram(DDR0_10, 0x00000300); |
| 544 | mtsdram(DDR0_11, 0x000CC800); |
| 545 | mtsdram(DDR0_12, 0x00000003); |
| 546 | mtsdram(DDR0_14, 0x00000000); |
| 547 | mtsdram(DDR0_17, 0x1e000000); |
| 548 | mtsdram(DDR0_18, 0x1e1e1e1e); |
| 549 | mtsdram(DDR0_19, 0x1e1e1e1e); |
| 550 | mtsdram(DDR0_20, 0x0B0B0B0B); |
| 551 | mtsdram(DDR0_21, 0x0B0B0B0B); |
| 552 | #ifdef CONFIG_DDR_ECC |
| 553 | mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ |
| 554 | #else |
| 555 | mtsdram(DDR0_22, 0x00267F0B); |
| 556 | #endif |
| 557 | |
| 558 | mtsdram(DDR0_23, 0x01000000); |
| 559 | mtsdram(DDR0_24, 0x01010001); |
| 560 | |
| 561 | mtsdram(DDR0_26, 0x2D93028A); |
| 562 | mtsdram(DDR0_27, 0x0784682B); |
| 563 | |
| 564 | mtsdram(DDR0_28, 0x00000080); |
| 565 | mtsdram(DDR0_31, 0x00000000); |
| 566 | mtsdram(DDR0_42, 0x01000006); |
| 567 | |
| 568 | mtsdram(DDR0_43, 0x030A0200); |
| 569 | mtsdram(DDR0_44, 0x00000003); |
| 570 | mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ |
Stefan Roese | 04e6c38 | 2007-07-04 10:06:30 +0200 | [diff] [blame] | 571 | #else |
| 572 | /* CL=4 */ |
| 573 | mtsdram(DDR0_02, 0x00000000); |
| 574 | |
| 575 | mtsdram(DDR0_00, 0x0000190A); |
| 576 | mtsdram(DDR0_01, 0x01000000); |
| 577 | mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ |
| 578 | |
| 579 | mtsdram(DDR0_04, 0x0B030300); |
| 580 | mtsdram(DDR0_05, 0x02020308); |
| 581 | mtsdram(DDR0_06, 0x0003C812); |
| 582 | mtsdram(DDR0_07, 0x00090100); |
| 583 | mtsdram(DDR0_08, 0x03c80001); |
| 584 | mtsdram(DDR0_09, 0x00011D5F); |
| 585 | mtsdram(DDR0_10, 0x00000300); |
| 586 | mtsdram(DDR0_11, 0x000CC800); |
| 587 | mtsdram(DDR0_12, 0x00000003); |
| 588 | mtsdram(DDR0_14, 0x00000000); |
| 589 | mtsdram(DDR0_17, 0x1e000000); |
| 590 | mtsdram(DDR0_18, 0x1e1e1e1e); |
| 591 | mtsdram(DDR0_19, 0x1e1e1e1e); |
| 592 | mtsdram(DDR0_20, 0x0B0B0B0B); |
| 593 | mtsdram(DDR0_21, 0x0B0B0B0B); |
| 594 | #ifdef CONFIG_DDR_ECC |
| 595 | mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ |
| 596 | #else |
| 597 | mtsdram(DDR0_22, 0x00267F0B); |
| 598 | #endif |
| 599 | |
| 600 | mtsdram(DDR0_23, 0x01000000); |
| 601 | mtsdram(DDR0_24, 0x01010001); |
| 602 | |
| 603 | mtsdram(DDR0_26, 0x2D93028A); |
| 604 | mtsdram(DDR0_27, 0x0784682B); |
| 605 | |
| 606 | mtsdram(DDR0_28, 0x00000080); |
| 607 | mtsdram(DDR0_31, 0x00000000); |
| 608 | mtsdram(DDR0_42, 0x01000008); |
| 609 | |
| 610 | mtsdram(DDR0_43, 0x050A0200); |
| 611 | mtsdram(DDR0_44, 0x00000005); |
| 612 | mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ |
| 613 | #endif |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 614 | |
| 615 | wait_for_dlllock(); |
| 616 | |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 617 | /* |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 618 | * Program tlb entries for this size (dynamic) |
| 619 | */ |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 620 | program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 621 | |
| 622 | /* |
| 623 | * Setup 2nd TLB with same physical address but different virtual address |
| 624 | * with cache enabled. This is done for fast ECC generation. |
| 625 | */ |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 626 | program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 627 | |
| 628 | #ifdef CONFIG_DDR_DATA_EYE |
| 629 | /* |
| 630 | * Perform data eye search if requested. |
| 631 | */ |
| 632 | denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 633 | #endif |
| 634 | |
| 635 | #ifdef CONFIG_DDR_ECC |
| 636 | /* |
| 637 | * If ECC is enabled, initialize the parity bits. |
| 638 | */ |
| 639 | program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); |
| 640 | #endif |
| 641 | |
Stefan Roese | ea9f6bc | 2007-07-31 08:37:01 +0200 | [diff] [blame] | 642 | /* |
| 643 | * Clear possible errors resulting from data-eye-search. |
| 644 | * If not done, then we could get an interrupt later on when |
| 645 | * exceptions are enabled. |
| 646 | */ |
| 647 | set_mcsr(get_mcsr()); |
| 648 | |
Stefan Roese | b765ffb | 2007-06-15 08:18:01 +0200 | [diff] [blame] | 649 | return (CFG_MBYTES_SDRAM << 20); |
| 650 | } |