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Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26/*
27 * CPU test
28 * Binary instructions instr rD,rA
29 *
30 * Logic instructions: neg
31 * Arithmetic instructions: addme, addze, subfme, subfze
32
33 * The test contains a pre-built table of instructions, operands and
34 * expected results. For each table entry, the test will cyclically use
35 * different sets of operand registers and result registers.
36 */
37
38#ifdef CONFIG_POST
39
40#include <post.h>
41#include "cpu_asm.h"
42
43#if CONFIG_POST & CFG_POST_CPU
44
45extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
46extern ulong cpu_post_makecr (long v);
47
48static struct cpu_post_two_s
49{
50 ulong cmd;
51 ulong op;
52 ulong res;
53} cpu_post_two_table[] =
54{
55 {
56 OP_NEG,
57 3,
58 -3
59 },
60 {
61 OP_NEG,
62 5,
63 -5
64 },
65 {
66 OP_ADDME,
67 6,
68 5
69 },
70 {
71 OP_ADDZE,
72 5,
73 5
74 },
75 {
76 OP_SUBFME,
77 6,
78 ~6 - 1
79 },
80 {
81 OP_SUBFZE,
82 5,
83 ~5
84 },
85};
86static unsigned int cpu_post_two_size =
87 sizeof (cpu_post_two_table) / sizeof (struct cpu_post_two_s);
88
89int cpu_post_test_two (void)
90{
91 int ret = 0;
92 unsigned int i, reg;
93 int flag = disable_interrupts();
94
95 for (i = 0; i < cpu_post_two_size && ret == 0; i++)
96 {
97 struct cpu_post_two_s *test = cpu_post_two_table + i;
98
99 for (reg = 0; reg < 32 && ret == 0; reg++)
100 {
101 unsigned int reg0 = (reg + 0) % 32;
102 unsigned int reg1 = (reg + 1) % 32;
103 unsigned int stk = reg < 16 ? 31 : 15;
104 unsigned long code[] =
105 {
106 ASM_STW(stk, 1, -4),
107 ASM_ADDI(stk, 1, -16),
108 ASM_STW(3, stk, 8),
109 ASM_STW(reg0, stk, 4),
110 ASM_STW(reg1, stk, 0),
111 ASM_LWZ(reg0, stk, 8),
112 ASM_11(test->cmd, reg1, reg0),
113 ASM_STW(reg1, stk, 8),
114 ASM_LWZ(reg1, stk, 0),
115 ASM_LWZ(reg0, stk, 4),
116 ASM_LWZ(3, stk, 8),
117 ASM_ADDI(1, stk, 16),
118 ASM_LWZ(stk, 1, -4),
119 ASM_BLR,
120 };
121 unsigned long codecr[] =
122 {
123 ASM_STW(stk, 1, -4),
124 ASM_ADDI(stk, 1, -16),
125 ASM_STW(3, stk, 8),
126 ASM_STW(reg0, stk, 4),
127 ASM_STW(reg1, stk, 0),
128 ASM_LWZ(reg0, stk, 8),
129 ASM_11(test->cmd, reg1, reg0) | BIT_C,
130 ASM_STW(reg1, stk, 8),
131 ASM_LWZ(reg1, stk, 0),
132 ASM_LWZ(reg0, stk, 4),
133 ASM_LWZ(3, stk, 8),
134 ASM_ADDI(1, stk, 16),
135 ASM_LWZ(stk, 1, -4),
136 ASM_BLR,
137 };
138 ulong res;
139 ulong cr;
140
141 if (ret == 0)
142 {
143 cr = 0;
144 cpu_post_exec_21 (code, & cr, & res, test->op);
145
146 ret = res == test->res && cr == 0 ? 0 : -1;
147
148 if (ret != 0)
149 {
150 post_log ("Error at two test %d !\n", i);
151 }
152 }
153
154 if (ret == 0)
155 {
156 cpu_post_exec_21 (codecr, & cr, & res, test->op);
157
158 ret = res == test->res &&
159 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
160
161 if (ret != 0)
162 {
163 post_log ("Error at two test %d !\n", i);
164 }
165 }
166 }
167 }
168
169 if (flag)
170 enable_interrupts();
171
172 return ret;
173}
174
175#endif
176#endif