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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b3b6ddff0bb6768af7532da4cee5362fbe41ec4b / . / arch / arm / cpu / tegra114-common / pinmux.c
blob: 16368c5bc114f8e84cbcf6c959b74e07bf357f76 [file] [log] [blame]
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra114 pin multiplexing functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/tegra.h>
22#include <asm/arch/pinmux.h>
23
24struct tegra_pingroup_desc {
25 const char *name;
26 enum pmux_func funcs[4];
27 enum pmux_func func_safe;
28 enum pmux_vddio vddio;
29 enum pmux_pin_io io;
30};
31
32#define PMUX_MUXCTL_SHIFT 0
33#define PMUX_PULL_SHIFT 2
34#define PMUX_TRISTATE_SHIFT 4
35#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
36#define PMUX_IO_SHIFT 5
37#define PMUX_OD_SHIFT 6
38#define PMUX_LOCK_SHIFT 7
39#define PMUX_IO_RESET_SHIFT 8
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]40#define PMUX_RCV_SEL_SHIFT 9
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]41
42/* Convenient macro for defining pin group properties */
43#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
44 { \
45 .vddio = PMUX_VDDIO_ ## vdd, \
46 .funcs = { \
47 PMUX_FUNC_ ## f0, \
48 PMUX_FUNC_ ## f1, \
49 PMUX_FUNC_ ## f2, \
50 PMUX_FUNC_ ## f3, \
51 }, \
52 .func_safe = PMUX_FUNC_RSVD1, \
53 .io = PMUX_PIN_ ## iod, \
54 }
55
56/* Input and output pins */
57#define PINI(pg_name, vdd, f0, f1, f2, f3) \
58 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
59#define PINO(pg_name, vdd, f0, f1, f2, f3) \
60 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
61
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]62/* A pin group number which is not used */
63#define PIN_RESERVED \
64 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
65
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]66const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
67 /* NAME VDD f0 f1 f2 f3 */
68 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
69 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
70 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
71 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
72 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
73 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
74 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
75 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
76 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
77 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
78 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
79 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
80 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
81 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
82 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
83 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
84 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
85 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
86 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
87 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
88 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
89 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
90 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
91 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]92 PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
93 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]94 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
95 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]96 PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
97 PIN_RESERVED,
98 PIN_RESERVED,
99 PIN_RESERVED,
100 PIN_RESERVED,
101 PIN_RESERVED,
102 PIN_RESERVED,
103 PIN_RESERVED,
104 PIN_RESERVED,
105 PIN_RESERVED,
106 PIN_RESERVED,
107 PIN_RESERVED,
108 PIN_RESERVED,
109 PIN_RESERVED,
110 PIN_RESERVED,
111 PIN_RESERVED,
112 PIN_RESERVED,
113 PIN_RESERVED,
114 PIN_RESERVED,
115 PIN_RESERVED,
116 PIN_RESERVED,
117 PIN_RESERVED,
118 PIN_RESERVED,
119 PIN_RESERVED,
120 PIN_RESERVED,
121 PIN_RESERVED,
122 PIN_RESERVED,
123 PIN_RESERVED,
124 PIN_RESERVED,
125 PIN_RESERVED,
126 PIN_RESERVED,
127 PIN_RESERVED,
128 PIN_RESERVED,
129 PIN_RESERVED,
130 PIN_RESERVED,
131 PIN_RESERVED,
132 PIN_RESERVED,
133 PIN_RESERVED,
134 PIN_RESERVED,
135 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]136 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
137 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
138 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]139 PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
140 PIN_RESERVED,
141 PIN_RESERVED,
142 PIN_RESERVED,
143 PIN_RESERVED,
144 PIN_RESERVED,
145 PIN_RESERVED,
146 PIN_RESERVED,
147 PIN_RESERVED,
148 PIN_RESERVED,
149 PIN_RESERVED,
150 PIN_RESERVED,
151 PIN_RESERVED,
152 PIN_RESERVED,
153 PIN_RESERVED,
154 PIN_RESERVED,
155 PIN_RESERVED,
156 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]157 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
158 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
159 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
160 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
161 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
162 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
163 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
164 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
165 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
166 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
167 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
168 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
169 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
170 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
171 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
172 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
173 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
174 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
175 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
176 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
177 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
178 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
179 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
180 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
181 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
182 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
183 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
184 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
185 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
186 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
187 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
188 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
189 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
190 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
191 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
192 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
193 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
194 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
195 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
196 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
197 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
198 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
199 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
200 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
201 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
202 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
203 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
204 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
205 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
206 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
207 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
208 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
209 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
210 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
211 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
212 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
213 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
214 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
215 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
216 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
217 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
218 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
219 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
220 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
221 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
222 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
223 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
224 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
225 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
226 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
227 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]228 PIN_RESERVED, /* Reserved by t114: 0x3280 */
Tom Warrenb3b6ddf2013-03-13 15:00:54 -0700[diff] [blame^]229 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]230 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
231 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
232 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
233 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
234 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
235 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
236 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
237 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
238 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
239 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
240 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
241 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
242 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
243 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
244 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
245 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
246 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
247 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
248 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
249 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
250 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
251 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
252 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
253 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]254 PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
255 PIN_RESERVED,
256 PIN_RESERVED,
257 PIN_RESERVED,
258 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]259 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
260 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
261 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
262 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
263 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
264 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
265 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
266 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
267 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
268 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
269 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
270 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
271 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
272 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
273 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
274 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
275 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
276 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
277 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
278 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
279 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
280 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
281 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
282 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
283 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
284 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
285 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]286 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
287 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
288 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
289 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
290 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
291 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
292 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
293 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
294 PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
295 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]296 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
297 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
298 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
299 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
300 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
301 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]302 PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
303 PIN_RESERVED,
304 PIN_RESERVED,
305 PIN_RESERVED,
306 PIN_RESERVED,
307 PIN_RESERVED,
308 PIN_RESERVED,
309 PIN_RESERVED,
310 PIN_RESERVED,
311 PIN_RESERVED,
312 PIN_RESERVED,
313 PIN_RESERVED,
314 PIN_RESERVED,
315 PIN_RESERVED,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]316 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
317 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]318 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
319 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
320 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
321 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
322 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]323 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]324 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
325 PIN_RESERVED, /* Reserved by t114: 0x3404 */
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]326 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
327};
328
329void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
330{
331 struct pmux_tri_ctlr *pmt =
332 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
333 u32 *tri = &pmt->pmt_ctl[pin];
334 u32 reg;
335
336 /* Error check on pin */
337 assert(pmux_pingrp_isvalid(pin));
338
339 reg = readl(tri);
340 if (enable)
341 reg |= PMUX_TRISTATE_MASK;
342 else
343 reg &= ~PMUX_TRISTATE_MASK;
344 writel(reg, tri);
345}
346
347void pinmux_tristate_enable(enum pmux_pingrp pin)
348{
349 pinmux_set_tristate(pin, 1);
350}
351
352void pinmux_tristate_disable(enum pmux_pingrp pin)
353{
354 pinmux_set_tristate(pin, 0);
355}
356
357void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
358{
359 struct pmux_tri_ctlr *pmt =
360 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
361 u32 *pull = &pmt->pmt_ctl[pin];
362 u32 reg;
363
364 /* Error check on pin and pupd */
365 assert(pmux_pingrp_isvalid(pin));
366 assert(pmux_pin_pupd_isvalid(pupd));
367
368 reg = readl(pull);
369 reg &= ~(0x3 << PMUX_PULL_SHIFT);
370 reg |= (pupd << PMUX_PULL_SHIFT);
371 writel(reg, pull);
372}
373
374void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
375{
376 struct pmux_tri_ctlr *pmt =
377 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
378 u32 *muxctl = &pmt->pmt_ctl[pin];
379 int i, mux = -1;
380 u32 reg;
381
382 /* Error check on pin and func */
383 assert(pmux_pingrp_isvalid(pin));
384 assert(pmux_func_isvalid(func));
385
386 /* Handle special values */
387 if (func == PMUX_FUNC_SAFE)
388 func = tegra_soc_pingroups[pin].func_safe;
389
390 if (func & PMUX_FUNC_RSVD1) {
391 mux = func & 0x3;
392 } else {
393 /* Search for the appropriate function */
394 for (i = 0; i < 4; i++) {
395 if (tegra_soc_pingroups[pin].funcs[i] == func) {
396 mux = i;
397 break;
398 }
399 }
400 }
401 assert(mux != -1);
402
403 reg = readl(muxctl);
404 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
405 reg |= (mux << PMUX_MUXCTL_SHIFT);
406 writel(reg, muxctl);
407
408}
409
410void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
411{
412 struct pmux_tri_ctlr *pmt =
413 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
414 u32 *pin_io = &pmt->pmt_ctl[pin];
415 u32 reg;
416
417 /* Error check on pin and io */
418 assert(pmux_pingrp_isvalid(pin));
419 assert(pmux_pin_io_isvalid(io));
420
421 reg = readl(pin_io);
422 reg &= ~(0x1 << PMUX_IO_SHIFT);
423 reg |= (io & 0x1) << PMUX_IO_SHIFT;
424 writel(reg, pin_io);
425}
426
427static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
428{
429 struct pmux_tri_ctlr *pmt =
430 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
431 u32 *pin_lock = &pmt->pmt_ctl[pin];
432 u32 reg;
433
434 /* Error check on pin and lock */
435 assert(pmux_pingrp_isvalid(pin));
436 assert(pmux_pin_lock_isvalid(lock));
437
438 if (lock == PMUX_PIN_LOCK_DEFAULT)
439 return 0;
440
441 reg = readl(pin_lock);
442 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
443 if (lock == PMUX_PIN_LOCK_ENABLE)
444 reg |= (0x1 << PMUX_LOCK_SHIFT);
445 else {
446 /* lock == DISABLE, which isn't possible */
447 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
448 __func__, lock);
449 }
450 writel(reg, pin_lock);
451
452 return 0;
453}
454
455static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
456{
457 struct pmux_tri_ctlr *pmt =
458 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
459 u32 *pin_od = &pmt->pmt_ctl[pin];
460 u32 reg;
461
462 /* Error check on pin and od */
463 assert(pmux_pingrp_isvalid(pin));
464 assert(pmux_pin_od_isvalid(od));
465
466 if (od == PMUX_PIN_OD_DEFAULT)
467 return 0;
468
469 reg = readl(pin_od);
470 reg &= ~(0x1 << PMUX_OD_SHIFT);
471 if (od == PMUX_PIN_OD_ENABLE)
472 reg |= (0x1 << PMUX_OD_SHIFT);
473 writel(reg, pin_od);
474
475 return 0;
476}
477
478static int pinmux_set_ioreset(enum pmux_pingrp pin,
479 enum pmux_pin_ioreset ioreset)
480{
481 struct pmux_tri_ctlr *pmt =
482 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
483 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
484 u32 reg;
485
486 /* Error check on pin and ioreset */
487 assert(pmux_pingrp_isvalid(pin));
488 assert(pmux_pin_ioreset_isvalid(ioreset));
489
490 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
491 return 0;
492
493 reg = readl(pin_ioreset);
494 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
495 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
496 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
497 writel(reg, pin_ioreset);
498
499 return 0;
500}
501
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]502static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
503 enum pmux_pin_rcv_sel rcv_sel)
504{
505 struct pmux_tri_ctlr *pmt =
506 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
507 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
508 u32 reg;
509
510 /* Error check on pin and rcv_sel */
511 assert(pmux_pingrp_isvalid(pin));
512 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
513
514 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
515 return 0;
516
517 reg = readl(pin_rcv_sel);
518 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
519 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
520 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
521 writel(reg, pin_rcv_sel);
522
523 return 0;
524}
525
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]526void pinmux_config_pingroup(struct pingroup_config *config)
527{
528 enum pmux_pingrp pin = config->pingroup;
529
530 pinmux_set_func(pin, config->func);
531 pinmux_set_pullupdown(pin, config->pull);
532 pinmux_set_tristate(pin, config->tristate);
533 pinmux_set_io(pin, config->io);
534 pinmux_set_lock(pin, config->lock);
535 pinmux_set_od(pin, config->od);
536 pinmux_set_ioreset(pin, config->ioreset);
Tom Warren8b7776b2013-03-01 14:38:20 -0700[diff] [blame]537 pinmux_set_rcv_sel(pin, config->rcv_sel);
Tom Warrene23bb6a2013-01-28 13:32:10 +0000[diff] [blame]538}
539
540void pinmux_config_table(struct pingroup_config *config, int len)
541{
542 int i;
543
544 for (i = 0; i < len; i++)
545 pinmux_config_pingroup(&config[i]);
546}