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Tom Rixe63e5902009-10-17 12:41:06 -05001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the 3430 TI SDP3430 board.
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Tom Rixe63e5902009-10-17 12:41:06 -050011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* TODO: REMOVE THE FOLLOWING
17 * Retained the following till size.h is removed in u-boot
18 */
Alexey Brodkin1ace4022014-02-26 17:47:58 +040019#include <linux/sizes.h>
Tom Rixe63e5902009-10-17 12:41:06 -050020/*
21 * High Level Configuration Options
22 */
Tom Rixe63e5902009-10-17 12:41:06 -050023#define CONFIG_OMAP 1 /* in a TI OMAP core */
Tom Rixe63e5902009-10-17 12:41:06 -050024#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
Lokesh Vutla806d2792013-07-30 11:36:30 +053025#define CONFIG_OMAP_COMMON
Tom Rixe63e5902009-10-17 12:41:06 -050026
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040027#define CONFIG_SDRC /* The chip has SDRC controller */
28
Tom Rixe63e5902009-10-17 12:41:06 -050029#include <asm/arch/cpu.h> /* get chip and board defs */
30#include <asm/arch/omap3.h>
31
32/*
33 * NOTE: these #defines presume standard SDP jumper settings.
34 * In particular:
35 * - 26 MHz clock (not 19.2 or 38.4 MHz)
36 * - Boot from 128MB NOR, not NAND or OneNAND
37 *
38 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
39 * support for all the flash types the board supports.
40 */
41#define CONFIG_DISPLAY_CPUINFO 1
42#define CONFIG_DISPLAY_BOARDINFO 1
43
44/* Clock Defines */
45#define V_OSCK 26000000 /* Clock output from T2 */
46#define V_SCLK (V_OSCK >> 1)
47
Tom Rixe63e5902009-10-17 12:41:06 -050048#define CONFIG_MISC_INIT_R
49
50#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
51#define CONFIG_SETUP_MEMORY_TAGS 1
52#define CONFIG_INITRD_TAG 1
53#define CONFIG_REVISION_TAG 1
54
Grant Likely2fa8ca92011-03-28 09:59:07 +000055#define CONFIG_OF_LIBFDT 1
56
Tom Rixe63e5902009-10-17 12:41:06 -050057/*
58 * Size of malloc() pool
59 * Total Size Environment - 256k
60 * Malloc - add 256k
61 */
62#define CONFIG_ENV_SIZE (256 << 10)
63#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Tom Rixe63e5902009-10-17 12:41:06 -050064
65/*--------------------------------------------------------------------------*/
66
67/*
68 * Hardware drivers
69 */
70
71/*
72 * TWL4030
73 */
74#define CONFIG_TWL4030_POWER 1
75
76/*
77 * serial port - NS16550 compatible
78 */
79#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85
86/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
87 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
88 * support UART boot (that's only for UART3); it prevents sharing a Linux
89 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
90 *
91 * UART boot uses UART3 on J9, and the SDP user's guide says to use
92 * that for console. Downsides of using J9: you can't use IRDA too;
93 * since UART3 isn't in the CORE power domain, it may be a bit less
94 * usable in certain PM-sensitive debug scenarios.
95 */
96#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
97
98#ifdef CONSOLE_J9
99#define CONFIG_CONS_INDEX 3
100#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
101#define CONFIG_SERIAL3 3 /* UART3 */
102#else
103#define CONFIG_CONS_INDEX 1
104#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
105#define CONFIG_SERIAL1 1 /* UART1 */
106#endif
107
108#define CONFIG_ENV_OVERWRITE
109#define CONFIG_BAUDRATE 115200
110#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
111 115200}
112
113/*
114 * I2C for power management setup
115 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200116#define CONFIG_SYS_I2C
117#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
118#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
119#define CONFIG_SYS_I2C_OMAP34XX
Tom Rixe63e5902009-10-17 12:41:06 -0500120
Tom Rixe63e5902009-10-17 12:41:06 -0500121/* OMITTED: single 1 Gbit MT29F1G NAND flash */
122
123/*
124 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
125 */
126#define CONFIG_SYS_FLASH_BASE 0x10000000
127#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
128#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
130#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
131#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
132#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
134
135#define CONFIG_SYS_FLASH_CFI_WIDTH 2
136#define PHYS_FLASH_SIZE (128 << 20)
137#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
138
Tom Rixe63e5902009-10-17 12:41:06 -0500139/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
140
141#define CONFIG_ENV_IS_IN_FLASH 1
142#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
143#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
144#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
145/*--------------------------------------------------------------------------*/
146
147/* commands to include */
148#include <config_cmd_default.h>
149
150/* Enabled commands */
151#define CONFIG_CMD_DHCP /* DHCP Support */
152#define CONFIG_CMD_EXT2 /* EXT2 Support */
153#define CONFIG_CMD_FAT /* FAT support */
154#define CONFIG_CMD_I2C /* I2C serial bus support */
155#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
156#define CONFIG_CMD_MMC /* MMC support */
157#define CONFIG_CMD_NET
158
159/* Disabled commands */
160#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
161#undef CONFIG_CMD_IMLS /* List all found images */
162
163/*--------------------------------------------------------------------------*/
164/*
165 * MMC boot support
166 */
167
168#if defined(CONFIG_CMD_MMC)
Tom Rini7cc862b2011-09-03 21:52:21 -0400169#define CONFIG_GENERIC_MMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500170#define CONFIG_MMC 1
Tom Rini7cc862b2011-09-03 21:52:21 -0400171#define CONFIG_OMAP_HSMMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500172#define CONFIG_DOS_PARTITION 1
173#endif
174
175/*----------------------------------------------------------------------------
176 * SMSC9115 Ethernet from SMSC9118 family
177 *----------------------------------------------------------------------------
178 */
179#if defined(CONFIG_CMD_NET)
180
Nishanth Menona1725992009-10-16 00:06:36 -0500181#define CONFIG_LAN91C96
Tom Rixe63e5902009-10-17 12:41:06 -0500182#define CONFIG_LAN91C96_BASE DEBUG_BASE
183#define CONFIG_LAN91C96_EXT_PHY
184
185#define CONFIG_BOOTP_SEND_HOSTNAME
186/*
187 * BOOTP fields
188 */
189#define CONFIG_BOOTP_SUBNETMASK 0x00000001
190#define CONFIG_BOOTP_GATEWAY 0x00000002
191#define CONFIG_BOOTP_HOSTNAME 0x00000004
192#define CONFIG_BOOTP_BOOTPATH 0x00000010
193#endif /* (CONFIG_CMD_NET) */
194
195/*
196 * Environment setup
197 *
198 * Default boot order: mmc bootscript, MMC uImage, NOR image.
199 * Network booting environment must be configured at site.
200 */
201
202/* allow overwriting serial config and ethaddr */
203#define CONFIG_ENV_OVERWRITE
204
205#define CONFIG_EXTRA_ENV_SETTINGS \
206 "loadaddr=0x82000000\0" \
207 "console=ttyS0,115200n8\0" \
208 "mmcargs=setenv bootargs console=${console} " \
209 "root=/dev/mmcblk0p2 rw " \
210 "rootfstype=ext3 rootwait\0" \
211 "norargs=setenv bootargs console=${console} " \
212 "root=/dev/mtdblock3 rw " \
213 "rootfstype=jffs2\0" \
214 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
215 "bootscript=echo Running bootscript from MMC/SD ...; " \
216 "autoscr ${loadaddr}\0" \
217 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
218 "mmcboot=echo Booting from MMC/SD ...; " \
219 "run mmcargs; " \
220 "bootm ${loadaddr}\0" \
221 "norboot=echo Booting from NOR ...; " \
222 "run norargs; " \
223 "bootm 0x80000\0" \
224
225#define CONFIG_BOOTCOMMAND \
226 "if mmcinit; then " \
227 "if run loadbootscript; then " \
228 "run bootscript; " \
229 "else " \
230 "if run loaduimage; then " \
231 "run mmcboot; " \
232 "else run norboot; " \
233 "fi; " \
234 "fi; " \
235 "else run norboot; fi"
236
237#define CONFIG_AUTO_COMPLETE 1
238
239/*--------------------------------------------------------------------------*/
240
241/*
242 * Miscellaneous configurable options
243 */
Tom Rixe63e5902009-10-17 12:41:06 -0500244
245#define CONFIG_SYS_LONGHELP /* undef to save memory */
246#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500247#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
Vaibhav Hiremathf62b1252011-09-03 21:24:19 -0400248#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Tom Rixe63e5902009-10-17 12:41:06 -0500249/* Print Buffer Size */
250#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
251 sizeof(CONFIG_SYS_PROMPT) + 16)
252#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
253/* Boot Argument Buffer Size */
254#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
255
256/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
257 * a basic sanity check ONLY
258 * IF you would like to increase coverage, increase the end address
259 * or run the test with custom options
260 */
261#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
262#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
263
264/* Default load address */
265#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
266
267/*--------------------------------------------------------------------------*/
268
269/*
270 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
271 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
272 */
273#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
274#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Tom Rixe63e5902009-10-17 12:41:06 -0500275
Dirk Behme5ec789f2010-11-30 11:10:40 -0500276#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
277#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
278#define CONFIG_SYS_INIT_RAM_SIZE 0x800
279#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
280 CONFIG_SYS_INIT_RAM_SIZE - \
281 GENERATED_GBL_DATA_SIZE)
Tom Rixe63e5902009-10-17 12:41:06 -0500282/*
283 * SDRAM Memory Map
284 */
285#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
286#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Tom Rixe63e5902009-10-17 12:41:06 -0500287#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
288
Tom Rixe63e5902009-10-17 12:41:06 -0500289/*--------------------------------------------------------------------------*/
290
291/*
292 * NOR FLASH usage ... default nCS0:
293 * - one 256KB sector for U-Boot
294 * - one 256KB sector for its parameters (not all used)
295 * - eight sectors (2 MB) for kernel
296 * - rest for JFFS2
297 */
298
299/* Monitor at start of flash */
300#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
301#define CONFIG_SYS_MONITOR_LEN (256 << 10)
302
Tom Rixe63e5902009-10-17 12:41:06 -0500303/*
304 * NAND FLASH usage ... default nCS1:
305 * - four 128KB sectors for X-Loader
306 * - four 128KB sectors for U-Boot
307 * - two 128KB sector for its parameters
308 * - 32 sectors (4 MB) for kernel
309 * - rest for filesystem
310 */
311
312/*
313 * OneNAND FLASH usage ... default nCS2:
314 * - four 128KB sectors for X-Loader
315 * - two 128KB sectors for U-Boot
316 * - one 128KB sector for its parameters
317 * - sixteen sectors (2 MB) for kernel
318 * - rest for filesystem
319 */
320
Aneesh V8e408522011-11-21 23:38:59 +0000321#define CONFIG_SYS_CACHELINE_SIZE 64
322
Tom Rixe63e5902009-10-17 12:41:06 -0500323#endif /* __CONFIG_H */