blob: d509e30d35901505d19966d87f0eaa06a8ea6352 [file] [log] [blame]
Andy Fleming9082eea2011-04-07 21:56:05 -05001/*
2 * Atheros PHY drivers
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05005 *
Xie Xiaobo60273842013-04-10 16:23:39 +08006 * Copyright 2011, 2013 Freescale Semiconductor, Inc.
Andy Fleming9082eea2011-04-07 21:56:05 -05007 * author Andy Fleming
Andy Fleming9082eea2011-04-07 21:56:05 -05008 */
9#include <phy.h>
10
11static int ar8021_config(struct phy_device *phydev)
12{
13 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
14 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
15
Zhao Qiange0d80962013-12-23 15:51:33 +080016 phydev->supported = phydev->drv->features;
Andy Fleming9082eea2011-04-07 21:56:05 -050017 return 0;
18}
19
Xie Xiaobo60273842013-04-10 16:23:39 +080020static int ar8035_config(struct phy_device *phydev)
21{
22 int regval;
23
24 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
25 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
26 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
27 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
28 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
29
30 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
31 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
32 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
33
Xiaobo Xie02aa4c52014-04-11 16:03:11 +080034 phydev->supported = phydev->drv->features;
Xie Xiaobo60273842013-04-10 16:23:39 +080035
36 return 0;
37}
38
Kim Phillips06370592012-10-29 13:34:33 +000039static struct phy_driver AR8021_driver = {
Andy Fleming9082eea2011-04-07 21:56:05 -050040 .name = "AR8021",
41 .uid = 0x4dd040,
Haijun.Zhangdc116bd2014-03-04 15:56:12 +080042 .mask = 0x4ffff0,
Andy Fleming9082eea2011-04-07 21:56:05 -050043 .features = PHY_GBIT_FEATURES,
44 .config = ar8021_config,
45 .startup = genphy_startup,
46 .shutdown = genphy_shutdown,
47};
48
Heiko Schocher433a2c52013-06-04 10:58:00 +020049static struct phy_driver AR8031_driver = {
Shengzhou Liu626ee1e2013-08-08 16:33:35 +080050 .name = "AR8031/AR8033",
Heiko Schocher433a2c52013-06-04 10:58:00 +020051 .uid = 0x4dd074,
Fabio Estevamf66e3de2014-01-03 15:55:59 -020052 .mask = 0xffffffef,
Heiko Schocher433a2c52013-06-04 10:58:00 +020053 .features = PHY_GBIT_FEATURES,
Zhao Qiang08ad9b02014-04-21 10:29:24 +080054 .config = ar8021_config,
Heiko Schocher433a2c52013-06-04 10:58:00 +020055 .startup = genphy_startup,
56 .shutdown = genphy_shutdown,
57};
58
59static struct phy_driver AR8035_driver = {
Xie Xiaobo60273842013-04-10 16:23:39 +080060 .name = "AR8035",
61 .uid = 0x4dd072,
Fabio Estevamf66e3de2014-01-03 15:55:59 -020062 .mask = 0xffffffef,
Xie Xiaobo60273842013-04-10 16:23:39 +080063 .features = PHY_GBIT_FEATURES,
64 .config = ar8035_config,
65 .startup = genphy_startup,
66 .shutdown = genphy_shutdown,
67};
68
Andy Fleming9082eea2011-04-07 21:56:05 -050069int phy_atheros_init(void)
70{
71 phy_register(&AR8021_driver);
Heiko Schocher433a2c52013-06-04 10:58:00 +020072 phy_register(&AR8031_driver);
Xie Xiaobo60273842013-04-10 16:23:39 +080073 phy_register(&AR8035_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -050074
75 return 0;
76}