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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
Wolfgang Denk2ae18242010-10-06 09:05:45 +02002 * (C) Copyright 2006-2010
Marian Balakowicz991425f2006-03-14 16:24:38 +01003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz991425f2006-03-14 16:24:38 +01006 */
7
8/*
9 * mpc8349emds board configuration file
10 *
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Kim Phillipsfdfaa292015-03-17 12:00:45 -050016#define CONFIG_DISPLAY_BOARDINFO
17
Marian Balakowicz991425f2006-03-14 16:24:38 +010018/*
19 * High Level Configuration Options
20 */
21#define CONFIG_E300 1 /* E300 Family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050022#define CONFIG_MPC834x 1 /* MPC834x family */
Marian Balakowicz991425f2006-03-14 16:24:38 +010023#define CONFIG_MPC8349 1 /* MPC8349 specific */
24#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xFE000000
27
28#define CONFIG_PCI_66M
29#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010030#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
31#else
32#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
33#endif
34
Ira W. Snyder447ad572008-08-22 11:00:15 -070035#ifdef CONFIG_PCISLAVE
36#define CONFIG_PCI
37#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
38#endif /* CONFIG_PCISLAVE */
39
Marian Balakowicz991425f2006-03-14 16:24:38 +010040#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010042#define CONFIG_SYS_CLK_FREQ 66000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050043#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010044#else
45#define CONFIG_SYS_CLK_FREQ 33000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050046#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010047#endif
48#endif
49
50#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_IMMR 0xE0000000
Marian Balakowicz991425f2006-03-14 16:24:38 +010053
Joe Hershberger32795ec2011-10-11 23:57:14 -050054#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
56#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicz991425f2006-03-14 16:24:38 +010057
58/*
59 * DDR Setup
60 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +080061#define CONFIG_DDR_ECC /* support DDR ECC function */
Marian Balakowiczd326f4a2006-03-16 15:19:35 +010062#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Marian Balakowicz991425f2006-03-14 16:24:38 +010063#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
64
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010065/*
York Sun5614e712013-09-30 09:22:09 -070066 * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
York Sund4b91062011-08-26 11:32:45 -070067 * undefine it to use old spd_sdram.c
68 */
York Sun5614e712013-09-30 09:22:09 -070069#define CONFIG_SYS_FSL_DDR2
70#ifdef CONFIG_SYS_FSL_DDR2
York Sun1df99082013-12-03 13:16:59 -080071#define CONFIG_SYS_FSL_DDRC_GEN2
York Sund4b91062011-08-26 11:32:45 -070072#define CONFIG_SYS_SPD_BUS_NUM 0
73#define SPD_EEPROM_ADDRESS1 0x52
74#define SPD_EEPROM_ADDRESS2 0x51
75#define CONFIG_NUM_DDR_CONTROLLERS 1
76#define CONFIG_DIMM_SLOTS_PER_CTLR 2
77#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
78#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
79#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80#endif
81
82/*
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010083 * 32-bit data path mode.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020084 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010085 * Please note that using this mode for devices with the real density of 64-bit
86 * effectively reduces the amount of available memory due to the effect of
87 * wrapping around while translating address to row/columns, for example in the
88 * 256MB module the upper 128MB get aliased with contents of the lower
89 * 128MB); normally this define should be used for devices with real 32-bit
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020090 * data path.
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010091 */
92#undef CONFIG_DDR_32BIT
93
Joe Hershberger32795ec2011-10-11 23:57:14 -050094#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
95#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger32795ec2011-10-11 23:57:14 -050097#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
98 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Marian Balakowicz991425f2006-03-14 16:24:38 +010099#undef CONFIG_DDR_2T_TIMING
100
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800101/*
102 * DDRCDR - DDR Control Driver Register
103 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800105
Marian Balakowicz991425f2006-03-14 16:24:38 +0100106#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100107/*
108 * Determine DDR configuration from I2C interface.
109 */
110#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100111#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100112/*
113 * Manually set up DDR parameters
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800116#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_DDRCDR 0x80080001
Joe Hershberger32795ec2011-10-11 23:57:14 -0500118#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
Joe Hershberger32795ec2011-10-11 23:57:14 -0500120#define CONFIG_SYS_DDR_TIMING_0 0x00220802
121#define CONFIG_SYS_DDR_TIMING_1 0x38357322
122#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
123#define CONFIG_SYS_DDR_TIMING_3 0x00000000
124#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_DDR_MODE 0x47d00432
126#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500127#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
129#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800130#else
Joe Hershberger2e651b22011-10-11 23:57:31 -0500131#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500132 | CSCONFIG_ROW_BIT_13 \
133 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_DDR_TIMING_1 0x36332321
135#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500136#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100138
139#if defined(CONFIG_DDR_32BIT)
140/* set burst length to 8 for 32-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500141 /* DLL,normal,seq,4/2.5, 8 burst len */
142#define CONFIG_SYS_DDR_MODE 0x00000023
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100143#else
144/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500145 /* DLL,normal,seq,4/2.5, 4 burst len */
146#define CONFIG_SYS_DDR_MODE 0x00000022
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100147#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100148#endif
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800149#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100150
151/*
152 * SDRAM on the Local Bus
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
155#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100156
157/*
158 * FLASH on the Local Bus
159 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500160#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
161#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500163#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
164#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100166
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500167#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
168 | BR_PS_16 /* 16 bit port */ \
169 | BR_MS_GPCM /* MSEL = GPCM */ \
170 | BR_V) /* valid */
171#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500172 | OR_UPM_XAM \
173 | OR_GPCM_CSNT \
174 | OR_GPCM_ACS_DIV2 \
175 | OR_GPCM_XACS \
176 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500177 | OR_GPCM_TRLX_SET \
178 | OR_GPCM_EHTR_SET \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500179 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500180
Joe Hershberger32795ec2011-10-11 23:57:14 -0500181 /* window base at flash base */
182#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500183#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100184
Joe Hershberger32795ec2011-10-11 23:57:14 -0500185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
186#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#undef CONFIG_SYS_FLASH_CHECKSUM
189#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
190#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100191
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195#define CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100196#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#undef CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100198#endif
199
200/*
201 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
202 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500203#define CONFIG_SYS_BCSR 0xE2400000
204 /* Access window base at BCSR base */
205#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500206#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
207#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
208 | BR_PS_8 \
209 | BR_MS_GPCM \
210 | BR_V)
211 /* 0x00000801 */
212#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
213 | OR_GPCM_XAM \
214 | OR_GPCM_CSNT \
215 | OR_GPCM_SCY_15 \
216 | OR_GPCM_TRLX_CLEAR \
217 | OR_GPCM_EHTR_CLEAR)
218 /* 0xFFFFE8F0 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger32795ec2011-10-11 23:57:14 -0500221#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
222#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100223
Joe Hershberger32795ec2011-10-11 23:57:14 -0500224#define CONFIG_SYS_GBL_DATA_OFFSET \
225 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicz991425f2006-03-14 16:24:38 +0100227
Kevin Hao16c8c172016-07-08 11:25:14 +0800228#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500229#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100230
231/*
232 * Local Bus LCRR and LBCR regs
233 * LCRR: DLL bypass, Clock divider is 4
234 * External Local Bus rate is
235 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
236 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500237#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
238#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_LBC_LBCR 0x00000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100240
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800241/*
242 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#undef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#ifdef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100248/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
249/*
250 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100252 *
253 * For BR2, need:
254 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
255 * port-size = 32-bits = BR2[19:20] = 11
256 * no parity checking = BR2[21:22] = 00
257 * SDRAM for MSEL = BR2[24:26] = 011
258 * Valid = BR[31] = 1
259 *
260 * 0 4 8 12 16 20 24 28
261 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Marian Balakowicz991425f2006-03-14 16:24:38 +0100262 */
263
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
265 | BR_PS_32 /* 32-bit port */ \
266 | BR_MS_SDRAM /* MSEL = SDRAM */ \
267 | BR_V) /* Valid */
268 /* 0xF0001861 */
269#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
270#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100271
272/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100274 *
275 * For OR2, need:
276 * 64MB mask for AM, OR2[0:7] = 1111 1100
277 * XAM, OR2[17:18] = 11
278 * 9 columns OR2[19-21] = 010
279 * 13 rows OR2[23-25] = 100
280 * EAD set for extra time OR[31] = 1
281 *
282 * 0 4 8 12 16 20 24 28
283 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
284 */
285
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
287 | OR_SDRAM_XAM \
288 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
289 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
290 | OR_SDRAM_EAD)
291 /* 0xFC006901 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100292
Joe Hershberger32795ec2011-10-11 23:57:14 -0500293 /* LB sdram refresh timer, about 6us */
294#define CONFIG_SYS_LBC_LSRT 0x32000000
295 /* LB refresh timer prescal, 266MHz/32 */
296#define CONFIG_SYS_LBC_MRTPR 0x20000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100297
Joe Hershberger32795ec2011-10-11 23:57:14 -0500298#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
Kumar Gala540dcf12009-03-26 01:34:39 -0500299 | LSDMR_BSMA1516 \
300 | LSDMR_RFCR8 \
301 | LSDMR_PRETOACT6 \
302 | LSDMR_ACTTORW3 \
303 | LSDMR_BL8 \
304 | LSDMR_WRC3 \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500305 | LSDMR_CL3)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100306
307/*
308 * SDRAM Controller configuration sequence.
309 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500310#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
311#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
312#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
313#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
314#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100315#endif
316
317/*
318 * Serial Port
319 */
320#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_NS16550_SERIAL
322#define CONFIG_SYS_NS16550_REG_SIZE 1
323#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Marian Balakowicz991425f2006-03-14 16:24:38 +0100327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
329#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100330
Kim Phillips22d71a72007-02-27 18:41:08 -0600331#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500332#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100333
334/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200335#define CONFIG_SYS_I2C
336#define CONFIG_SYS_I2C_FSL
337#define CONFIG_SYS_FSL_I2C_SPEED 400000
338#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
339#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
340#define CONFIG_SYS_FSL_I2C2_SPEED 400000
341#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
342#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
343#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Marian Balakowicz991425f2006-03-14 16:24:38 +0100344
Ben Warren80ddd222008-01-16 22:37:42 -0500345/* SPI */
Ben Warren8931ab12008-01-26 23:41:19 -0500346#define CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500347#undef CONFIG_SOFT_SPI /* SPI bit-banged */
Ben Warren80ddd222008-01-16 22:37:42 -0500348
349/* GPIOs. Used as SPI chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_GPIO1_PRELIM
351#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
352#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
Ben Warren80ddd222008-01-16 22:37:42 -0500353
Marian Balakowicz991425f2006-03-14 16:24:38 +0100354/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500356#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500358#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100359
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500360/* USB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100362
363/*
364 * General PCI
365 * Addresses are mapped 1-1.
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
368#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
369#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
370#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
371#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
372#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500373#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
374#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
375#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
378#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
379#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
380#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
381#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
382#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500383#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
384#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
385#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100386
387#if defined(CONFIG_PCI)
388
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500389#define PCI_ONE_PCI1
Marian Balakowicz991425f2006-03-14 16:24:38 +0100390#if defined(PCI_64BIT)
391#undef PCI_ALL_PCI1
392#undef PCI_TWO_PCI1
393#undef PCI_ONE_PCI1
394#endif
395
Marian Balakowicz991425f2006-03-14 16:24:38 +0100396#define CONFIG_PCI_PNP /* do pci plug-and-play */
Ira W. Snyder162338e2008-08-22 11:00:13 -0700397#define CONFIG_83XX_PCI_STREAMING
Marian Balakowicz991425f2006-03-14 16:24:38 +0100398
399#undef CONFIG_EEPRO100
400#undef CONFIG_TULIP
401
402#if !defined(CONFIG_PCI_PNP)
403 #define PCI_ENET0_IOADDR 0xFIXME
404 #define PCI_ENET0_MEMADDR 0xFIXME
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200405 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100406#endif
407
408#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100410
411#endif /* CONFIG_PCI */
412
413/*
414 * TSEC configuration
415 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500416#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100417
418#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100419
420#define CONFIG_GMII 1 /* MII PHY management */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500421#define CONFIG_TSEC1 1
Kim Phillips255a35772007-05-16 16:52:19 -0500422#define CONFIG_TSEC1_NAME "TSEC0"
Joe Hershberger32795ec2011-10-11 23:57:14 -0500423#define CONFIG_TSEC2 1
Kim Phillips255a35772007-05-16 16:52:19 -0500424#define CONFIG_TSEC2_NAME "TSEC1"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100425#define TSEC1_PHY_ADDR 0
426#define TSEC2_PHY_ADDR 1
427#define TSEC1_PHYIDX 0
428#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500429#define TSEC1_FLAGS TSEC_GIGABIT
430#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100431
432/* Options are: TSEC[0-1] */
433#define CONFIG_ETHPRIME "TSEC0"
434
435#endif /* CONFIG_TSEC_ENET */
436
437/*
438 * Configure on-board RTC
439 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500440#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
441#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100442
443/*
444 * Environment
445 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200447 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger32795ec2011-10-11 23:57:14 -0500448 #define CONFIG_ENV_ADDR \
449 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200450 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
451 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100452
453/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200454#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
455#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100456
457#else
Joe Hershberger32795ec2011-10-11 23:57:14 -0500458 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200459 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200461 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100462#endif
463
464#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100466
Jon Loeliger8ea54992007-07-04 22:30:06 -0500467/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500468 * BOOTP options
469 */
470#define CONFIG_BOOTP_BOOTFILESIZE
471#define CONFIG_BOOTP_BOOTPATH
472#define CONFIG_BOOTP_GATEWAY
473#define CONFIG_BOOTP_HOSTNAME
474
Jon Loeliger659e2f62007-07-10 09:10:49 -0500475/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500476 * Command line configuration.
477 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500478#define CONFIG_CMD_DATE
Jon Loeliger8ea54992007-07-04 22:30:06 -0500479
Marian Balakowicz991425f2006-03-14 16:24:38 +0100480#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500481 #define CONFIG_CMD_PCI
Marian Balakowicz991425f2006-03-14 16:24:38 +0100482#endif
483
Marian Balakowicz991425f2006-03-14 16:24:38 +0100484#undef CONFIG_WATCHDOG /* watchdog disabled */
485
486/*
487 * Miscellaneous configurable options
488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_LONGHELP /* undef to save memory */
490#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100491
Jon Loeliger8ea54992007-07-04 22:30:06 -0500492#if defined(CONFIG_CMD_KGDB)
Joe Hershberger32795ec2011-10-11 23:57:14 -0500493 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100494#else
Joe Hershberger32795ec2011-10-11 23:57:14 -0500495 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100496#endif
497
Joe Hershberger32795ec2011-10-11 23:57:14 -0500498 /* Print Buffer Size */
499#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
500#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
501 /* Boot Argument Buffer Size */
502#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Marian Balakowicz991425f2006-03-14 16:24:38 +0100503
504/*
505 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700506 * have to be in the first 256 MB of memory, since this is
Marian Balakowicz991425f2006-03-14 16:24:38 +0100507 * the maximum mapped by the Linux kernel during initialization.
508 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500509 /* Initial Memory map for Linux*/
510#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800511#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100514
515#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100517 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
518 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500519 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100520 HRCWL_VCO_1X2 |\
521 HRCWL_CORE_TO_CSB_2X1)
522#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100524 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
525 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500526 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100527 HRCWL_VCO_1X4 |\
528 HRCWL_CORE_TO_CSB_3X1)
529#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100531 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
532 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500533 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100534 HRCWL_VCO_1X4 |\
535 HRCWL_CORE_TO_CSB_2X1)
536#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100538 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
539 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500540 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100541 HRCWL_VCO_1X4 |\
542 HRCWL_CORE_TO_CSB_1X1)
543#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100545 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
546 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500547 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100548 HRCWL_VCO_1X4 |\
549 HRCWL_CORE_TO_CSB_1X1)
550#endif
551
Ira W. Snyder447ad572008-08-22 11:00:15 -0700552#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_HRCW_HIGH (\
Ira W. Snyder447ad572008-08-22 11:00:15 -0700554 HRCWH_PCI_AGENT |\
555 HRCWH_64_BIT_PCI |\
556 HRCWH_PCI1_ARBITER_DISABLE |\
557 HRCWH_PCI2_ARBITER_DISABLE |\
558 HRCWH_CORE_ENABLE |\
559 HRCWH_FROM_0X00000100 |\
560 HRCWH_BOOTSEQ_DISABLE |\
561 HRCWH_SW_WATCHDOG_DISABLE |\
562 HRCWH_ROM_LOC_LOCAL_16BIT |\
563 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500564 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700565#else
Marian Balakowicz991425f2006-03-14 16:24:38 +0100566#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100568 HRCWH_PCI_HOST |\
569 HRCWH_64_BIT_PCI |\
570 HRCWH_PCI1_ARBITER_ENABLE |\
571 HRCWH_PCI2_ARBITER_DISABLE |\
572 HRCWH_CORE_ENABLE |\
573 HRCWH_FROM_0X00000100 |\
574 HRCWH_BOOTSEQ_DISABLE |\
575 HRCWH_SW_WATCHDOG_DISABLE |\
576 HRCWH_ROM_LOC_LOCAL_16BIT |\
577 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500578 HRCWH_TSEC2M_IN_GMII)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100579#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100581 HRCWH_PCI_HOST |\
582 HRCWH_32_BIT_PCI |\
583 HRCWH_PCI1_ARBITER_ENABLE |\
584 HRCWH_PCI2_ARBITER_ENABLE |\
585 HRCWH_CORE_ENABLE |\
586 HRCWH_FROM_0X00000100 |\
587 HRCWH_BOOTSEQ_DISABLE |\
588 HRCWH_SW_WATCHDOG_DISABLE |\
589 HRCWH_ROM_LOC_LOCAL_16BIT |\
590 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500591 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700592#endif /* PCI_64BIT */
593#endif /* CONFIG_PCISLAVE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100594
Lee Nippera5fe5142008-04-25 15:44:45 -0500595/*
596 * System performance
597 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500599#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
601#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
602#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
603#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Lee Nippera5fe5142008-04-25 15:44:45 -0500604
Marian Balakowicz991425f2006-03-14 16:24:38 +0100605/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500606#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_SICRL SICRL_LDP_A
Marian Balakowicz991425f2006-03-14 16:24:38 +0100608
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500610#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
611 | HID0_ENABLE_INSTRUCTION_CACHE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100612
Joe Hershberger32795ec2011-10-11 23:57:14 -0500613/* #define CONFIG_SYS_HID0_FINAL (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100614 HID0_ENABLE_INSTRUCTION_CACHE |\
615 HID0_ENABLE_M_BIT |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500616 HID0_ENABLE_ADDRESS_BROADCAST) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100617
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500619#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100620
621/* DDR @ 0x00000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500622#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500623 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500624 | BATL_MEMCOHERENCE)
625#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
626 | BATU_BL_256M \
627 | BATU_VS \
628 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100629
630/* PCI @ 0x80000000 */
631#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000632#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger32795ec2011-10-11 23:57:14 -0500633#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500634 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500635 | BATL_MEMCOHERENCE)
636#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
637 | BATU_BL_256M \
638 | BATU_VS \
639 | BATU_VP)
640#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500641 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500642 | BATL_CACHEINHIBIT \
643 | BATL_GUARDEDSTORAGE)
644#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
645 | BATU_BL_256M \
646 | BATU_VS \
647 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100648#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200649#define CONFIG_SYS_IBAT1L (0)
650#define CONFIG_SYS_IBAT1U (0)
651#define CONFIG_SYS_IBAT2L (0)
652#define CONFIG_SYS_IBAT2U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100653#endif
654
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500655#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger32795ec2011-10-11 23:57:14 -0500656#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500657 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500658 | BATL_MEMCOHERENCE)
659#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
660 | BATU_BL_256M \
661 | BATU_VS \
662 | BATU_VP)
663#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500664 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500665 | BATL_CACHEINHIBIT \
666 | BATL_GUARDEDSTORAGE)
667#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
668 | BATU_BL_256M \
669 | BATU_VS \
670 | BATU_VP)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500671#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_IBAT3L (0)
673#define CONFIG_SYS_IBAT3U (0)
674#define CONFIG_SYS_IBAT4L (0)
675#define CONFIG_SYS_IBAT4U (0)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500676#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100677
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500678/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500679#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500680 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500681 | BATL_CACHEINHIBIT \
682 | BATL_GUARDEDSTORAGE)
683#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
684 | BATU_BL_256M \
685 | BATU_VS \
686 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100687
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500688/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500689#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500690 | BATL_PP_RW \
691 | BATL_MEMCOHERENCE \
692 | BATL_GUARDEDSTORAGE)
Joe Hershberger32795ec2011-10-11 23:57:14 -0500693#define CONFIG_SYS_IBAT6U (0xF0000000 \
694 | BATU_BL_256M \
695 | BATU_VS \
696 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100697
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200698#define CONFIG_SYS_IBAT7L (0)
699#define CONFIG_SYS_IBAT7U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100700
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200701#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
702#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
703#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
704#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
705#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
706#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
707#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
708#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
709#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
710#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
711#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
712#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
713#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
714#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
715#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
716#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Marian Balakowicz991425f2006-03-14 16:24:38 +0100717
Jon Loeliger8ea54992007-07-04 22:30:06 -0500718#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100719#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100720#endif
721
722/*
723 * Environment Configuration
724 */
725#define CONFIG_ENV_OVERWRITE
726
727#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100728#define CONFIG_HAS_ETH1
Andy Fleming10327dc2007-08-16 16:35:02 -0500729#define CONFIG_HAS_ETH0
Marian Balakowicz991425f2006-03-14 16:24:38 +0100730#endif
731
Marian Balakowicz991425f2006-03-14 16:24:38 +0100732#define CONFIG_HOSTNAME mpc8349emds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000733#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000734#define CONFIG_BOOTFILE "uImage"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100735
Joe Hershberger32795ec2011-10-11 23:57:14 -0500736#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100737
Joe Hershberger32795ec2011-10-11 23:57:14 -0500738#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100739
740#define CONFIG_BAUDRATE 115200
741
742#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100743 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100744 "echo"
745
746#define CONFIG_EXTRA_ENV_SETTINGS \
747 "netdev=eth0\0" \
748 "hostname=mpc8349emds\0" \
749 "nfsargs=setenv bootargs root=/dev/nfs rw " \
750 "nfsroot=${serverip}:${rootpath}\0" \
751 "ramargs=setenv bootargs root=/dev/ram rw\0" \
752 "addip=setenv bootargs ${bootargs} " \
753 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
754 ":${hostname}:${netdev}:off panic=1\0" \
755 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
756 "flash_nfs=run nfsargs addip addtty;" \
757 "bootm ${kernel_addr}\0" \
758 "flash_self=run ramargs addip addtty;" \
759 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
760 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
761 "bootm\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100762 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
763 "update=protect off fe000000 fe03ffff; " \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500764 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100765 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500766 "fdtaddr=780000\0" \
Kim Phillipscc861f72009-08-26 21:25:46 -0500767 "fdtfile=mpc834x_mds.dtb\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100768 ""
769
Joe Hershberger32795ec2011-10-11 23:57:14 -0500770#define CONFIG_NFSBOOTCOMMAND \
771 "setenv bootargs root=/dev/nfs rw " \
772 "nfsroot=$serverip:$rootpath " \
773 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
774 "$netdev:off " \
775 "console=$consoledev,$baudrate $othbootargs;" \
776 "tftp $loadaddr $bootfile;" \
777 "tftp $fdtaddr $fdtfile;" \
778 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600779
780#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500781 "setenv bootargs root=/dev/ram rw " \
782 "console=$consoledev,$baudrate $othbootargs;" \
783 "tftp $ramdiskaddr $ramdiskfile;" \
784 "tftp $loadaddr $bootfile;" \
785 "tftp $fdtaddr $fdtfile;" \
786 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600787
Marian Balakowicz991425f2006-03-14 16:24:38 +0100788#define CONFIG_BOOTCOMMAND "run flash_self"
789
790#endif /* __CONFIG_H */