Chris Packham | c0def24 | 2016-09-22 12:56:14 +1200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree file for Marvell Armada 385 development board |
| 3 | * (DB-88F6820-AMC) |
| 4 | * |
| 5 | * Copyright (C) 2014 Marvell |
| 6 | * |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| 8 | * |
| 9 | * This file is dual-licensed: you can use it either under the terms |
| 10 | * of the GPL or the X11 license, at your option. Note that this dual |
| 11 | * licensing only applies to this file, and not this project as a |
| 12 | * whole. |
| 13 | * |
| 14 | * a) This file is licensed under the terms of the GNU General Public |
| 15 | * License version 2. This program is licensed "as is" without |
| 16 | * any warranty of any kind, whether express or implied. |
| 17 | * |
| 18 | * Or, alternatively, |
| 19 | * |
| 20 | * b) Permission is hereby granted, free of charge, to any person |
| 21 | * obtaining a copy of this software and associated documentation |
| 22 | * files (the "Software"), to deal in the Software without |
| 23 | * restriction, including without limitation the rights to use, |
| 24 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 25 | * sell copies of the Software, and to permit persons to whom the |
| 26 | * Software is furnished to do so, subject to the following |
| 27 | * conditions: |
| 28 | * |
| 29 | * The above copyright notice and this permission notice shall be |
| 30 | * included in all copies or substantial portions of the Software. |
| 31 | * |
| 32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 33 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 34 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 35 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 36 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 37 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 39 | * OTHER DEALINGS IN THE SOFTWARE. |
| 40 | */ |
| 41 | |
| 42 | /dts-v1/; |
| 43 | #include "armada-385.dtsi" |
| 44 | #include <dt-bindings/gpio/gpio.h> |
| 45 | |
| 46 | / { |
| 47 | model = "Marvell Armada 385 AMC"; |
| 48 | compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; |
| 49 | |
| 50 | chosen { |
| 51 | stdout-path = "serial0:115200n8"; |
| 52 | }; |
| 53 | |
| 54 | aliases { |
| 55 | ethernet0 = ð0; |
Chris Packham | 0a05bf4 | 2018-01-08 16:17:12 +1300 | [diff] [blame] | 56 | ethernet1 = ð2; |
Chris Packham | e38f5fc | 2017-05-02 20:35:25 +1200 | [diff] [blame] | 57 | i2c0 = &i2c0; |
Chris Packham | c0def24 | 2016-09-22 12:56:14 +1200 | [diff] [blame] | 58 | spi1 = &spi1; |
| 59 | }; |
| 60 | |
| 61 | memory { |
| 62 | device_type = "memory"; |
| 63 | reg = <0x00000000 0x80000000>; /* 2 GB */ |
| 64 | }; |
| 65 | |
| 66 | soc { |
| 67 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
| 68 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; |
| 69 | |
| 70 | internal-regs { |
| 71 | i2c@11000 { |
Chris Packham | e38f5fc | 2017-05-02 20:35:25 +1200 | [diff] [blame] | 72 | clock-frequency = <100000>; |
| 73 | u-boot,i2c-slave-addr = <0x0>; |
Chris Packham | c0def24 | 2016-09-22 12:56:14 +1200 | [diff] [blame] | 74 | pinctrl-names = "default"; |
| 75 | pinctrl-0 = <&i2c0_pins>; |
| 76 | status = "okay"; |
| 77 | }; |
| 78 | |
| 79 | serial@12000 { |
| 80 | /* |
| 81 | * Exported on the micro USB connector CON16 |
| 82 | * through an FTDI |
| 83 | */ |
| 84 | |
| 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&uart0_pins>; |
| 87 | status = "okay"; |
| 88 | u-boot,dm-pre-reloc; |
| 89 | }; |
| 90 | |
| 91 | ethernet@34000 { |
| 92 | status = "okay"; |
| 93 | phy = <&phy1>; |
| 94 | phy-mode = "sgmii"; |
| 95 | }; |
| 96 | |
| 97 | usb@58000 { |
| 98 | status = "okay"; |
| 99 | }; |
| 100 | |
| 101 | ethernet@70000 { |
| 102 | pinctrl-names = "default"; |
| 103 | /* |
| 104 | * The Reference Clock 0 is used to provide a |
| 105 | * clock to the PHY |
| 106 | */ |
| 107 | pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; |
| 108 | status = "okay"; |
| 109 | phy = <&phy0>; |
| 110 | phy-mode = "rgmii-id"; |
| 111 | }; |
| 112 | |
| 113 | |
| 114 | mdio@72004 { |
| 115 | pinctrl-names = "default"; |
| 116 | pinctrl-0 = <&mdio_pins>; |
| 117 | |
| 118 | phy0: ethernet-phy@1 { |
| 119 | reg = <1>; |
| 120 | }; |
| 121 | |
| 122 | phy1: ethernet-phy@0 { |
| 123 | reg = <0>; |
| 124 | }; |
| 125 | }; |
Chris Packham | 42f7505 | 2016-09-22 12:56:15 +1200 | [diff] [blame] | 126 | |
| 127 | flash@d0000 { |
| 128 | status = "okay"; |
| 129 | num-cs = <1>; |
| 130 | marvell,nand-keep-config; |
| 131 | marvell,nand-enable-arbiter; |
| 132 | nand-on-flash-bbt; |
| 133 | }; |
Chris Packham | c0def24 | 2016-09-22 12:56:14 +1200 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | pcie-controller { |
| 137 | status = "okay"; |
| 138 | pcie@1,0 { |
| 139 | /* Port 0, Lane 0 */ |
| 140 | status = "okay"; |
| 141 | }; |
| 142 | |
| 143 | }; |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | &spi1 { |
| 148 | pinctrl-names = "default"; |
| 149 | pinctrl-0 = <&spi1_pins>; |
| 150 | status = "okay"; |
| 151 | u-boot,dm-pre-reloc; |
| 152 | |
| 153 | spi-flash@0 { |
| 154 | u-boot,dm-pre-reloc; |
| 155 | #address-cells = <1>; |
| 156 | #size-cells = <1>; |
Chris Packham | dbc3e64 | 2017-08-29 20:37:54 +1200 | [diff] [blame] | 157 | compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; |
Chris Packham | c0def24 | 2016-09-22 12:56:14 +1200 | [diff] [blame] | 158 | reg = <0>; /* Chip select 0 */ |
| 159 | spi-max-frequency = <50000000>; |
| 160 | m25p,fast-read; |
| 161 | }; |
| 162 | }; |
| 163 | |
| 164 | &refclk { |
| 165 | clock-frequency = <20000000>; |
| 166 | }; |