blob: 7ece038c8fe45ece87d47b0f3400b7f7f9053a5b [file] [log] [blame]
Simon Glass5852d532016-01-21 19:45:04 -07001/*
2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <display.h>
11#include <dm.h>
12#include <edid.h>
13#include <panel.h>
14#include <regmap.h>
15#include <syscon.h>
16#include <asm/gpio.h>
17#include <asm/io.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/edp_rk3288.h>
20#include <asm/arch/grf_rk3288.h>
21#include <dt-bindings/clock/rk3288-cru.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define MAX_CR_LOOP 5
26#define MAX_EQ_LOOP 5
27#define DP_LINK_STATUS_SIZE 6
28
29static const char * const voltage_names[] = {
30 "0.4V", "0.6V", "0.8V", "1.2V"
31};
32static const char * const pre_emph_names[] = {
33 "0dB", "3.5dB", "6dB", "9.5dB"
34};
35
36#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
37#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
38
39struct rk_edp_priv {
40 struct rk3288_edp *regs;
41 struct rk3288_grf *grf;
42 struct udevice *panel;
43 struct link_train link_train;
44 u8 train_set[4];
45};
46
47static void rk_edp_init_refclk(struct rk3288_edp *regs)
48{
49 writel(SEL_24M, &regs->analog_ctl_2);
50 writel(REF_CLK_24M, &regs->pll_reg_1);
51
52 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
53 V2L_CUR_SEL_1MA, &regs->pll_reg_2);
54
55 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
56 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
57 &regs->pll_reg_3);
58
59 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
60 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
61 &regs->pll_reg_5);
62
63 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
64
65 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
66 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
67 &regs->tx_common);
68
69 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
70 &regs->dp_aux);
71
72 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
73 &regs->dp_bias);
74
75 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
76 &regs->dp_reserv2);
77}
78
79static void rk_edp_init_interrupt(struct rk3288_edp *regs)
80{
81 /* Set interrupt pin assertion polarity as high */
82 writel(INT_POL, &regs->int_ctl);
83
84 /* Clear pending registers */
85 writel(0xff, &regs->common_int_sta_1);
86 writel(0x4f, &regs->common_int_sta_2);
87 writel(0xff, &regs->common_int_sta_3);
88 writel(0x27, &regs->common_int_sta_4);
89 writel(0x7f, &regs->dp_int_sta);
90
91 /* 0:mask,1: unmask */
92 writel(0x00, &regs->common_int_mask_1);
93 writel(0x00, &regs->common_int_mask_2);
94 writel(0x00, &regs->common_int_mask_3);
95 writel(0x00, &regs->common_int_mask_4);
96 writel(0x00, &regs->int_sta_mask);
97}
98
99static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
100{
101 clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
102}
103
104static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
105{
106 u32 val;
107
108 val = readl(&regs->dp_debug_ctl);
109
110 return val & PLL_LOCK;
111}
112
113static int rk_edp_init_analog_func(struct rk3288_edp *regs)
114{
115 ulong start;
116
117 writel(0x00, &regs->dp_pd);
118 writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
119
120 clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
121
122 start = get_timer(0);
123 while (!rk_edp_get_pll_locked(regs)) {
124 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
125 printf("%s: PLL is not locked\n", __func__);
126 return -ETIMEDOUT;
127 }
128 }
129
130 /* Enable Serdes FIFO function and Link symbol clock domain module */
131 clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
132 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
133 SSC_FUNC_EN_N);
134
135 return 0;
136}
137
138static void rk_edp_init_aux(struct rk3288_edp *regs)
139{
140 /* Clear inerrupts related to AUX channel */
141 writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
142
143 /* Disable AUX channel module */
144 setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
145
146 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
147 writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
148
149 /* Enable AUX channel module */
150 clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
151}
152
153static int rk_edp_aux_enable(struct rk3288_edp *regs)
154{
155 ulong start;
156
157 setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
158 start = get_timer(0);
159 do {
160 if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
161 return 0;
162 } while (get_timer(start) < 20);
163
164 return -ETIMEDOUT;
165}
166
167static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
168{
169 ulong start;
170
171 start = get_timer(0);
172 while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
173 if (get_timer(start) > 10)
174 return -ETIMEDOUT;
175 }
176
177 writel(RPLY_RECEIV, &regs->dp_int_sta);
178
179 return 0;
180}
181
182static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
183{
184 int val, ret;
185
186 /* Enable AUX CH operation */
187 ret = rk_edp_aux_enable(regs);
188 if (ret) {
189 debug("AUX CH enable timeout!\n");
190 return ret;
191 }
192
193 /* Is AUX CH command reply received? */
194 if (rk_edp_is_aux_reply(regs)) {
195 debug("AUX CH command reply failed!\n");
196 return ret;
197 }
198
199 /* Clear interrupt source for AUX CH access error */
200 val = readl(&regs->dp_int_sta);
201 if (val & AUX_ERR) {
202 writel(AUX_ERR, &regs->dp_int_sta);
203 return -EIO;
204 }
205
206 /* Check AUX CH error access status */
207 val = readl(&regs->dp_int_sta);
208 if (val & AUX_STATUS_MASK) {
209 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
210 return -EIO;
211 }
212
213 return 0;
214}
215
216static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
217 unsigned int val_addr, u8 *in_data,
218 unsigned int length,
219 enum dpcd_request request)
220{
221 int val;
222 int i, try_times;
223 u8 *data;
224 int ret = 0;
225 u32 len = 0;
226
227 while (length) {
228 len = min(length, 16U);
229 for (try_times = 0; try_times < 10; try_times++) {
230 data = in_data;
231 /* Clear AUX CH data buffer */
232 writel(BUF_CLR, &regs->buf_data_ctl);
233
234 /* Select DPCD device address */
235 writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
236 writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
237 writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
238
239 /*
240 * Set DisplayPort transaction and read 1 byte
241 * If bit 3 is 1, DisplayPort transaction.
242 * If Bit 3 is 0, I2C transaction.
243 */
244 if (request == DPCD_WRITE) {
245 val = AUX_LENGTH(len) |
246 AUX_TX_COMM_DP_TRANSACTION |
247 AUX_TX_COMM_WRITE;
248 for (i = 0; i < len; i++)
249 writel(*data++, &regs->buf_data[i]);
250 } else
251 val = AUX_LENGTH(len) |
252 AUX_TX_COMM_DP_TRANSACTION |
253 AUX_TX_COMM_READ;
254
255 writel(val, &regs->aux_ch_ctl_1);
256
257 /* Start AUX transaction */
258 ret = rk_edp_start_aux_transaction(regs);
259 if (ret == 0)
260 break;
261 else
262 printf("read dpcd Aux Transaction fail!\n");
263 }
264
265 if (ret)
266 return ret;
267
268 if (request == DPCD_READ) {
269 for (i = 0; i < len; i++)
270 *data++ = (u8)readl(&regs->buf_data[i]);
271 }
272
273 length -= len;
274 val_addr += len;
275 in_data += len;
276 }
277
278 return 0;
279}
280
281static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
282 size_t size)
283{
284 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
285}
286
287static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
288 size_t size)
289{
290 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
291}
292
293
294static int rk_edp_link_power_up(struct rk_edp_priv *edp)
295{
296 u8 value;
297 int ret;
298
299 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
300 if (edp->link_train.revision < 0x11)
301 return 0;
302
303 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
304 if (ret)
305 return ret;
306
307 value &= ~DP_SET_POWER_MASK;
308 value |= DP_SET_POWER_D0;
309
310 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
311 if (ret)
312 return ret;
313
314 /*
315 * According to the DP 1.1 specification, a "Sink Device must exit the
316 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
317 * Control Field" (register 0x600).
318 */
319 mdelay(1);
320
321 return 0;
322}
323
324static int rk_edp_link_configure(struct rk_edp_priv *edp)
325{
326 u8 values[2];
327
328 values[0] = edp->link_train.link_rate;
329 values[1] = edp->link_train.lane_count;
330
331 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
332 sizeof(values));
333}
334
335static void rk_edp_set_link_training(struct rk_edp_priv *edp,
336 const u8 *training_values)
337{
338 int i;
339
340 for (i = 0; i < edp->link_train.lane_count; i++)
341 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
342}
343
344static u8 edp_link_status(const u8 *link_status, int r)
345{
346 return link_status[r - DPCD_LANE0_1_STATUS];
347}
348
349static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
350 u8 *link_status)
351{
352 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
353 DP_LINK_STATUS_SIZE);
354}
355
356static u8 edp_get_lane_status(const u8 *link_status, int lane)
357{
358 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
359 int s = (lane & 1) * 4;
360 u8 l = edp_link_status(link_status, i);
361
362 return (l >> s) & 0xf;
363}
364
365static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
366{
367 int lane;
368 u8 lane_status;
369
370 for (lane = 0; lane < lane_count; lane++) {
371 lane_status = edp_get_lane_status(link_status, lane);
372 if ((lane_status & DP_LANE_CR_DONE) == 0)
373 return -EIO;
374 }
375
376 return 0;
377}
378
379static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
380{
381 u8 lane_align;
382 u8 lane_status;
383 int lane;
384
385 lane_align = edp_link_status(link_status,
386 DPCD_LANE_ALIGN_STATUS_UPDATED);
387 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
388 return -EIO;
389 for (lane = 0; lane < lane_count; lane++) {
390 lane_status = edp_get_lane_status(link_status, lane);
391 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
392 return -EIO;
393 }
394
395 return 0;
396}
397
398static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
399{
400 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
401 int s = ((lane & 1) ?
402 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
403 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
404 u8 l = edp_link_status(link_status, i);
405
406 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
407}
408
409static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
410 int lane)
411{
412 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
413 int s = ((lane & 1) ?
414 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
415 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
416 u8 l = edp_link_status(link_status, i);
417
418 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
419}
420
421static void edp_get_adjust_train(const u8 *link_status, int lane_count,
422 u8 train_set[])
423{
424 uint v = 0;
425 uint p = 0;
426 int lane;
427
428 for (lane = 0; lane < lane_count; lane++) {
429 uint this_v, this_p;
430
431 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
432 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
433 lane);
434
435 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
436 lane,
437 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
438 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
439
440 if (this_v > v)
441 v = this_v;
442 if (this_p > p)
443 p = this_p;
444 }
445
446 if (v >= DP_VOLTAGE_MAX)
447 v |= DP_TRAIN_MAX_SWING_REACHED;
448
449 if (p >= DP_PRE_EMPHASIS_MAX)
450 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
451
452 debug("using signal parameters: voltage %s pre_emph %s\n",
453 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
454 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
455 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
456 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
457
458 for (lane = 0; lane < 4; lane++)
459 train_set[lane] = v | p;
460}
461
462static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
463{
464 struct rk3288_edp *regs = edp->regs;
465 int clock_recovery;
466 uint voltage, tries = 0;
467 u8 status[DP_LINK_STATUS_SIZE];
468 int i, ret;
469 u8 value;
470
471 value = DP_TRAINING_PATTERN_1;
472 writel(value, &regs->dp_training_ptn_set);
473 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
474 if (ret)
475 return ret;
476 memset(edp->train_set, '\0', sizeof(edp->train_set));
477
478 /* clock recovery loop */
479 clock_recovery = 0;
480 tries = 0;
481 voltage = 0xff;
482
483 while (1) {
484 rk_edp_set_link_training(edp, edp->train_set);
485 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
486 edp->train_set,
487 edp->link_train.lane_count);
488 if (ret)
489 return ret;
490
491 mdelay(1);
492
493 ret = rk_edp_dpcd_read_link_status(edp, status);
494 if (ret) {
495 printf("displayport link status failed, ret=%d\n", ret);
496 break;
497 }
498
499 clock_recovery = rk_edp_clock_recovery(status,
500 edp->link_train.lane_count);
501 if (!clock_recovery)
502 break;
503
504 for (i = 0; i < edp->link_train.lane_count; i++) {
505 if ((edp->train_set[i] &
506 DP_TRAIN_MAX_SWING_REACHED) == 0)
507 break;
508 }
509 if (i == edp->link_train.lane_count) {
510 printf("clock recovery reached max voltage\n");
511 break;
512 }
513
514 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
515 voltage) {
516 if (++tries == MAX_CR_LOOP) {
517 printf("clock recovery tried 5 times\n");
518 break;
519 }
520 } else {
521 tries = 0;
522 }
523
524 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
525
526 /* Compute new train_set as requested by sink */
527 edp_get_adjust_train(status, edp->link_train.lane_count,
528 edp->train_set);
529 }
530 if (clock_recovery) {
531 printf("clock recovery failed: %d\n", clock_recovery);
532 return clock_recovery;
533 } else {
534 debug("clock recovery at voltage %d pre-emphasis %d\n",
535 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
536 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
537 DP_TRAIN_PRE_EMPHASIS_SHIFT);
538 return 0;
539 }
540}
541
542static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
543{
544 struct rk3288_edp *regs = edp->regs;
545 int channel_eq;
546 u8 value;
547 int tries;
548 u8 status[DP_LINK_STATUS_SIZE];
549 int ret;
550
551 value = DP_TRAINING_PATTERN_2;
552 writel(value, &regs->dp_training_ptn_set);
553 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
554 if (ret)
555 return ret;
556
557 /* channel equalization loop */
558 channel_eq = 0;
559 for (tries = 0; tries < 5; tries++) {
560 rk_edp_set_link_training(edp, edp->train_set);
561 udelay(400);
562
563 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
564 printf("displayport link status failed\n");
565 return -1;
566 }
567
568 channel_eq = rk_edp_channel_eq(status,
569 edp->link_train.lane_count);
570 if (!channel_eq)
571 break;
572 edp_get_adjust_train(status, edp->link_train.lane_count,
573 edp->train_set);
574 }
575
576 if (channel_eq) {
577 printf("channel eq failed, ret=%d\n", channel_eq);
578 return channel_eq;
579 }
580
581 debug("channel eq at voltage %d pre-emphasis %d\n",
582 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
583 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
584 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
585
586 return 0;
587}
588
589static int rk_edp_init_training(struct rk_edp_priv *edp)
590{
591 u8 values[3];
592 int ret;
593
594 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
595 sizeof(values));
596 if (ret < 0)
597 return ret;
598
599 edp->link_train.revision = values[0];
600 edp->link_train.link_rate = values[1];
601 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
602
603 debug("max link rate:%d.%dGps max number of lanes:%d\n",
604 edp->link_train.link_rate * 27 / 100,
605 edp->link_train.link_rate * 27 % 100,
606 edp->link_train.lane_count);
607
608 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
609 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
610 debug("Rx Max Link Rate is abnormal :%x\n",
611 edp->link_train.link_rate);
612 return -EPERM;
613 }
614
615 if (edp->link_train.lane_count == 0) {
616 debug("Rx Max Lane count is abnormal :%x\n",
617 edp->link_train.lane_count);
618 return -EPERM;
619 }
620
621 ret = rk_edp_link_power_up(edp);
622 if (ret)
623 return ret;
624
625 return rk_edp_link_configure(edp);
626}
627
628static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
629{
630 ulong start;
631 u32 val;
632 int ret;
633
634 /* Set link rate and count as you want to establish */
635 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
636 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
637
638 ret = rk_edp_link_train_cr(edp);
639 if (ret)
640 return ret;
641 ret = rk_edp_link_train_ce(edp);
642 if (ret)
643 return ret;
644
645 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
646 start = get_timer(0);
647 do {
648 val = readl(&edp->regs->dp_hw_link_training);
649 if (!(val & HW_LT_EN))
650 break;
651 } while (get_timer(start) < 10);
652
653 if (val & HW_LT_ERR_CODE_MASK) {
654 printf("edp hw link training error: %d\n",
655 val >> HW_LT_ERR_CODE_SHIFT);
656 return -EIO;
657 }
658
659 return 0;
660}
661
662static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
663 unsigned int device_addr,
664 unsigned int val_addr)
665{
666 int ret;
667
668 /* Set EDID device address */
669 writel(device_addr, &regs->aux_addr_7_0);
670 writel(0x0, &regs->aux_addr_15_8);
671 writel(0x0, &regs->aux_addr_19_16);
672
673 /* Set offset from base address of EDID device */
674 writel(val_addr, &regs->buf_data[0]);
675
676 /*
677 * Set I2C transaction and write address
678 * If bit 3 is 1, DisplayPort transaction.
679 * If Bit 3 is 0, I2C transaction.
680 */
681 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
682 AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
683
684 /* Start AUX transaction */
685 ret = rk_edp_start_aux_transaction(regs);
686 if (ret != 0) {
687 debug("select_i2c_device Aux Transaction fail!\n");
688 return ret;
689 }
690
691 return 0;
692}
693
694static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
695 unsigned int val_addr, unsigned int count, u8 edid[])
696{
697 u32 val;
698 unsigned int i, j;
699 unsigned int cur_data_idx;
700 unsigned int defer = 0;
701 int ret = 0;
702
703 for (i = 0; i < count; i += 16) {
704 for (j = 0; j < 10; j++) { /* try 10 times */
705 /* Clear AUX CH data buffer */
706 writel(BUF_CLR, &regs->buf_data_ctl);
707
708 /* Set normal AUX CH command */
709 clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
710
711 /*
712 * If Rx sends defer, Tx sends only reads
713 * request without sending addres
714 */
715 if (!defer) {
716 ret = rk_edp_select_i2c_device(regs,
717 device_addr,
718 val_addr + i);
719 } else {
720 defer = 0;
721 }
722
723 /*
724 * Set I2C transaction and write data
725 * If bit 3 is 1, DisplayPort transaction.
726 * If Bit 3 is 0, I2C transaction.
727 */
728 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
729 AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
730
731 /* Start AUX transaction */
732 ret = rk_edp_start_aux_transaction(regs);
733 if (ret == 0) {
734 break;
735 } else {
736 debug("Aux Transaction fail!\n");
737 continue;
738 }
739
740 /* Check if Rx sends defer */
741 val = readl(&regs->aux_rx_comm);
742 if (val == AUX_RX_COMM_AUX_DEFER ||
743 val == AUX_RX_COMM_I2C_DEFER) {
744 debug("Defer: %d\n\n", val);
745 defer = 1;
746 }
747 }
748
749 if (ret)
750 return ret;
751
752 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
753 val = readl(&regs->buf_data[cur_data_idx]);
754 edid[i + cur_data_idx] = (u8)val;
755 }
756 }
757
758 return 0;
759}
760
761static int rk_edp_set_link_train(struct rk_edp_priv *edp)
762{
763 int ret;
764
765 ret = rk_edp_init_training(edp);
766 if (ret) {
767 printf("DP LT init failed!\n");
768 return ret;
769 }
770
771 ret = rk_edp_hw_link_training(edp);
772 if (ret)
773 return ret;
774
775 return 0;
776}
777
778static void rk_edp_init_video(struct rk3288_edp *regs)
779{
780 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
781 &regs->common_int_sta_1);
782 writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
783 writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
784}
785
786static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
787{
788 clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
789}
790
791static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
792 enum clock_recovery_m_value_type type,
793 u32 m_value,
794 u32 n_value)
795{
796 if (type == REGISTER_M) {
797 setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
798 writel(m_value & 0xff, &regs->m_vid_0);
799 writel((m_value >> 8) & 0xff, &regs->m_vid_1);
800 writel((m_value >> 16) & 0xff, &regs->m_vid_2);
801
802 writel(n_value & 0xf, &regs->n_vid_0);
803 writel((n_value >> 8) & 0xff, &regs->n_vid_1);
804 writel((n_value >> 16) & 0xff, &regs->n_vid_2);
805 } else {
806 clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
807
808 writel(0x00, &regs->n_vid_0);
809 writel(0x80, &regs->n_vid_1);
810 writel(0x00, &regs->n_vid_2);
811 }
812}
813
814static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
815{
816 ulong start;
817 u32 val;
818
819 start = get_timer(0);
820 do {
821 val = readl(&regs->sys_ctl_1);
822
823 /* must write value to update DET_STA bit status */
824 writel(val, &regs->sys_ctl_1);
825 val = readl(&regs->sys_ctl_1);
826 if (!(val & DET_STA))
827 continue;
828
829 val = readl(&regs->sys_ctl_2);
830
831 /* must write value to update CHA_STA bit status */
832 writel(val, &regs->sys_ctl_2);
833 val = readl(&regs->sys_ctl_2);
834 if (!(val & CHA_STA))
835 return 0;
836
837 } while (get_timer(start) < 100);
838
839 return -ETIMEDOUT;
840}
841
842static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
843{
844 ulong start;
845 u32 val;
846
847 start = get_timer(0);
848 do {
849 val = readl(&edp->regs->sys_ctl_3);
850
851 /* must write value to update STRM_VALID bit status */
852 writel(val, &edp->regs->sys_ctl_3);
853
854 val = readl(&edp->regs->sys_ctl_3);
855 if (!(val & STRM_VALID))
856 return 0;
857 } while (get_timer(start) < 100);
858
859 return -ETIMEDOUT;
860}
861
862static int rk_edp_config_video(struct rk_edp_priv *edp)
863{
864 int ret;
865
866 rk_edp_config_video_slave_mode(edp->regs);
867
868 if (!rk_edp_get_pll_locked(edp->regs)) {
869 debug("PLL is not locked yet.\n");
870 return -ETIMEDOUT;
871 }
872
873 ret = rk_edp_is_video_stream_clock_on(edp->regs);
874 if (ret)
875 return ret;
876
877 /* Set to use the register calculated M/N video */
878 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
879
880 /* For video bist, Video timing must be generated by register */
881 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
882
883 /* Disable video mute */
884 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
885
886 /* Enable video at next frame */
887 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
888
889 return rk_edp_is_video_stream_on(edp);
890}
891
892static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
893{
894 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
895}
896
897static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
898{
899 u32 val;
900
901 val = readl(&edp->regs->sys_ctl_3);
902 if (val & HPD_STATUS)
903 return 1;
904
905 return 0;
906}
907
908/*
909 * support edp HPD function
910 * some hardware version do not support edp hdp,
911 * we use 200ms to try to get the hpd single now,
912 * if we can not get edp hpd single, it will delay 200ms,
913 * also meet the edp power timing request, to compatible
914 * all of the hardware version
915 */
916static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
917{
918 ulong start;
919
920 start = get_timer(0);
921 do {
922 if (rockchip_edp_get_plug_in_status(edp))
923 return;
924 udelay(100);
925 } while (get_timer(start) < 200);
926
927 debug("do not get hpd single, force hpd\n");
928 rockchip_edp_force_hpd(edp);
929}
930
931static int rk_edp_enable(struct udevice *dev, int panel_bpp,
932 const struct display_timing *edid)
933{
934 struct rk_edp_priv *priv = dev_get_priv(dev);
935 int ret = 0;
936
937 ret = rk_edp_set_link_train(priv);
938 if (ret) {
939 printf("link train failed!\n");
940 return ret;
941 }
942
943 rk_edp_init_video(priv->regs);
944 ret = rk_edp_config_video(priv);
945 if (ret) {
946 printf("config video failed\n");
947 return ret;
948 }
949 ret = panel_enable_backlight(priv->panel);
950 if (ret) {
951 debug("%s: backlight error: %d\n", __func__, ret);
952 return ret;
953 }
954
955 return 0;
956}
957
958static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
959{
960 struct rk_edp_priv *priv = dev_get_priv(dev);
961 u32 edid_size = EDID_LENGTH;
962 int ret;
963 int i;
964
965 for (i = 0; i < 3; i++) {
966 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
967 EDID_LENGTH, &buf[EDID_HEADER]);
968 if (ret) {
969 debug("EDID read failed\n");
970 continue;
971 }
972
973 /*
974 * check if the EDID has an extension flag, and read additional
975 * EDID data if needed
976 */
977 if (buf[EDID_EXTENSION_FLAG]) {
978 edid_size += EDID_LENGTH;
979 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
980 EDID_LENGTH, EDID_LENGTH,
981 &buf[EDID_LENGTH]);
982 if (ret) {
983 debug("EDID Read failed!\n");
984 continue;
985 }
986 }
987 goto done;
988 }
989
990 /* After 3 attempts, give up */
991 return ret;
992
993done:
994 return edid_size;
995}
996
997static int rk_edp_ofdata_to_platdata(struct udevice *dev)
998{
999 struct rk_edp_priv *priv = dev_get_priv(dev);
1000
1001 priv->regs = (struct rk3288_edp *)dev_get_addr(dev);
1002 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1003
1004 return 0;
1005}
1006
1007int rk_edp_probe(struct udevice *dev)
1008{
1009 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1010 struct rk_edp_priv *priv = dev_get_priv(dev);
1011 struct rk3288_edp *regs = priv->regs;
Stephen Warren135aa952016-06-17 09:44:00 -06001012 struct clk clk;
Simon Glass5852d532016-01-21 19:45:04 -07001013 int ret;
1014
1015 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1016 &priv->panel);
1017 if (ret) {
1018 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1019 dev->name, ret);
1020 return ret;
1021 }
1022
1023 int vop_id = uc_plat->source_id;
1024 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1025
1026 ret = clk_get_by_index(dev, 1, &clk);
1027 if (ret >= 0) {
Stephen Warren135aa952016-06-17 09:44:00 -06001028 ret = clk_set_rate(&clk, 0);
1029 clk_free(&clk);
Simon Glass5852d532016-01-21 19:45:04 -07001030 }
1031 if (ret) {
1032 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1033 return ret;
1034 }
1035
1036 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1037 if (ret >= 0) {
Stephen Warren135aa952016-06-17 09:44:00 -06001038 ret = clk_set_rate(&clk, 192000000);
1039 clk_free(&clk);
Simon Glass5852d532016-01-21 19:45:04 -07001040 }
1041 if (ret < 0) {
1042 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1043 __func__, uc_plat->src_dev->name, ret);
1044 return ret;
1045 }
1046
1047 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1048 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1049
1050 /* select epd signal from vop0 or vop1 */
1051 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1052
1053 rockchip_edp_wait_hpd(priv);
1054
1055 rk_edp_init_refclk(regs);
1056 rk_edp_init_interrupt(regs);
1057 rk_edp_enable_sw_function(regs);
1058 ret = rk_edp_init_analog_func(regs);
1059 if (ret)
1060 return ret;
1061 rk_edp_init_aux(regs);
1062
1063 return 0;
1064}
1065
1066static const struct dm_display_ops dp_rockchip_ops = {
1067 .read_edid = rk_edp_read_edid,
1068 .enable = rk_edp_enable,
1069};
1070
1071static const struct udevice_id rockchip_dp_ids[] = {
1072 { .compatible = "rockchip,rk3288-edp" },
1073 { }
1074};
1075
1076U_BOOT_DRIVER(dp_rockchip) = {
1077 .name = "edp_rockchip",
1078 .id = UCLASS_DISPLAY,
1079 .of_match = rockchip_dp_ids,
1080 .ops = &dp_rockchip_ops,
1081 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1082 .probe = rk_edp_probe,
1083 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),
1084};