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wdenk2262cfe2002-11-18 00:14:45 +00001/*
wdenk8bde7f72003-06-27 21:31:46 +00002 *
wdenk2262cfe2002-11-18 00:14:45 +00003 * (C) Copyright 2002
4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/io.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000028#include <asm/pci.h>
wdenk2262cfe2002-11-18 00:14:45 +000029#include <asm/ic/sc520.h>
30#include <asm/ic/ali512x.h>
wdenkbdccc4f2003-08-05 17:43:17 +000031#include <spi.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000032
Wolfgang Denkd87080b2006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
34
wdenk7a8e9bed2003-05-31 18:35:21 +000035#undef SC520_CDP_DEBUG
36
37#ifdef SC520_CDP_DEBUG
38#define PRINTF(fmt,args...) printf (fmt ,##args)
39#else
40#define PRINTF(fmt,args...)
41#endif
wdenk2262cfe2002-11-18 00:14:45 +000042
43/* ------------------------------------------------------------------------- */
44
wdenk8bde7f72003-06-27 21:31:46 +000045
46/*
wdenk7a8e9bed2003-05-31 18:35:21 +000047 * Theory:
48 * We first set up all IRQs to be non-pci, edge triggered,
wdenk8bde7f72003-06-27 21:31:46 +000049 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
wdenk7a8e9bed2003-05-31 18:35:21 +000050 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
51 * as needed. Whe choose the irqs to gram from a configurable list
52 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
53 * such as 0 thngas will not work)
54 */
55
wdenk2262cfe2002-11-18 00:14:45 +000056static void irq_init(void)
57{
wdenk2262cfe2002-11-18 00:14:45 +000058 /* disable global interrupt mode */
wdenk8bde7f72003-06-27 21:31:46 +000059 write_mmcr_byte(SC520_PICICR, 0x40);
60
wdenk7a8e9bed2003-05-31 18:35:21 +000061 /* set all irqs to edge */
wdenk2262cfe2002-11-18 00:14:45 +000062 write_mmcr_byte(SC520_MPICMODE, 0x00);
wdenk7a8e9bed2003-05-31 18:35:21 +000063 write_mmcr_byte(SC520_SL1PICMODE, 0x00);
64 write_mmcr_byte(SC520_SL2PICMODE, 0x00);
wdenk8bde7f72003-06-27 21:31:46 +000065
66 /* active low polarity on PIC interrupt pins,
wdenk7a8e9bed2003-05-31 18:35:21 +000067 * active high polarity on all other irq pins */
68 write_mmcr_word(SC520_INTPINPOL, 0x0000);
wdenk2262cfe2002-11-18 00:14:45 +000069
70 /* set irq number mapping */
wdenk8bde7f72003-06-27 21:31:46 +000071 write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000072 write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
73 write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
wdenk8bde7f72003-06-27 21:31:46 +000074 write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
wdenk7a8e9bed2003-05-31 18:35:21 +000075 write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
76 write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
77 write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
78 write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
79 write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
80 write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
wdenk8bde7f72003-06-27 21:31:46 +000081 write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000082 write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */
83 write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
84 write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
85 write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
86 write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
87 write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
wdenk8bde7f72003-06-27 21:31:46 +000088
wdenk2262cfe2002-11-18 00:14:45 +000089 if (CFG_USE_SIO_UART) {
wdenk7a8e9bed2003-05-31 18:35:21 +000090 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
91 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
wdenk8bde7f72003-06-27 21:31:46 +000092 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
wdenk7a8e9bed2003-05-31 18:35:21 +000093 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
wdenk2262cfe2002-11-18 00:14:45 +000094 } else {
wdenk7a8e9bed2003-05-31 18:35:21 +000095 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
96 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
wdenk8bde7f72003-06-27 21:31:46 +000097 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */
wdenk7a8e9bed2003-05-31 18:35:21 +000098 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */
wdenk2262cfe2002-11-18 00:14:45 +000099 }
wdenk8bde7f72003-06-27 21:31:46 +0000100
wdenk7a8e9bed2003-05-31 18:35:21 +0000101 write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
102 write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
103 write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
104 write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
105 write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
106 write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
107 write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
108 write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
wdenk8bde7f72003-06-27 21:31:46 +0000109 write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
110
wdenk7a8e9bed2003-05-31 18:35:21 +0000111 write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
112 write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
wdenk8bde7f72003-06-27 21:31:46 +0000113
wdenk2262cfe2002-11-18 00:14:45 +0000114}
115
wdenk8bde7f72003-06-27 21:31:46 +0000116
wdenk2262cfe2002-11-18 00:14:45 +0000117/* PCI stuff */
118static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
119{
wdenk7a8e9bed2003-05-31 18:35:21 +0000120 /* a configurable lists of irqs to steal
121 * when we need one (a board with more pci interrupt pins
122 * would use a larger table */
123 static int irq_list[] = {
124 CFG_FIRST_PCI_IRQ,
125 CFG_SECOND_PCI_IRQ,
126 CFG_THIRD_PCI_IRQ,
127 CFG_FORTH_PCI_IRQ
128 };
129 static int next_irq_index=0;
wdenk8bde7f72003-06-27 21:31:46 +0000130
131 char tmp_pin;
wdenk7a8e9bed2003-05-31 18:35:21 +0000132 int pin;
wdenk8bde7f72003-06-27 21:31:46 +0000133
wdenk7a8e9bed2003-05-31 18:35:21 +0000134 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
135 pin = tmp_pin;
wdenk8bde7f72003-06-27 21:31:46 +0000136
wdenk7a8e9bed2003-05-31 18:35:21 +0000137 pin-=1; /* pci config space use 1-based numbering */
138 if (-1 == pin) {
139 return; /* device use no irq */
140 }
wdenk8bde7f72003-06-27 21:31:46 +0000141
142
wdenk7a8e9bed2003-05-31 18:35:21 +0000143 /* map device number + pin to a pin on the sc520 */
wdenk2262cfe2002-11-18 00:14:45 +0000144 switch (PCI_DEV(dev)) {
145 case 20:
wdenk7a8e9bed2003-05-31 18:35:21 +0000146 pin+=SC520_PCI_INTA;
wdenk2262cfe2002-11-18 00:14:45 +0000147 break;
wdenk8bde7f72003-06-27 21:31:46 +0000148
wdenk2262cfe2002-11-18 00:14:45 +0000149 case 19:
wdenk7a8e9bed2003-05-31 18:35:21 +0000150 pin+=SC520_PCI_INTB;
wdenk2262cfe2002-11-18 00:14:45 +0000151 break;
wdenk8bde7f72003-06-27 21:31:46 +0000152
wdenk2262cfe2002-11-18 00:14:45 +0000153 case 18:
wdenk7a8e9bed2003-05-31 18:35:21 +0000154 pin+=SC520_PCI_INTC;
wdenk2262cfe2002-11-18 00:14:45 +0000155 break;
wdenk8bde7f72003-06-27 21:31:46 +0000156
wdenk2262cfe2002-11-18 00:14:45 +0000157 case 17:
wdenk7a8e9bed2003-05-31 18:35:21 +0000158 pin+=SC520_PCI_INTD;
wdenk2262cfe2002-11-18 00:14:45 +0000159 break;
wdenk8bde7f72003-06-27 21:31:46 +0000160
161 default:
wdenk2262cfe2002-11-18 00:14:45 +0000162 return;
163 }
wdenk8bde7f72003-06-27 21:31:46 +0000164
wdenk7a8e9bed2003-05-31 18:35:21 +0000165 pin&=3; /* wrap around */
wdenk8bde7f72003-06-27 21:31:46 +0000166
wdenk7a8e9bed2003-05-31 18:35:21 +0000167 if (sc520_pci_ints[pin] == -1) {
wdenk8bde7f72003-06-27 21:31:46 +0000168 /* re-route one interrupt for us */
wdenk7a8e9bed2003-05-31 18:35:21 +0000169 if (next_irq_index > 3) {
170 return;
171 }
wdenk8bde7f72003-06-27 21:31:46 +0000172 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000173 return;
174 }
175 next_irq_index++;
176 }
177
wdenk8bde7f72003-06-27 21:31:46 +0000178
wdenk7a8e9bed2003-05-31 18:35:21 +0000179 if (-1 != sc520_pci_ints[pin]) {
wdenk8bde7f72003-06-27 21:31:46 +0000180 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
wdenk7a8e9bed2003-05-31 18:35:21 +0000181 sc520_pci_ints[pin]);
182 }
wdenk8bde7f72003-06-27 21:31:46 +0000183 PRINTF("fixup_irq: device %d pin %c irq %d\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000184 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
wdenk2262cfe2002-11-18 00:14:45 +0000185}
wdenk8bde7f72003-06-27 21:31:46 +0000186
wdenk2262cfe2002-11-18 00:14:45 +0000187static struct pci_controller sc520_cdp_hose = {
188 fixup_irq: pci_sc520_cdp_fixup_irq,
189};
190
stroesead10dd92003-02-14 11:21:23 +0000191void pci_init_board(void)
wdenk2262cfe2002-11-18 00:14:45 +0000192{
193 pci_sc520_init(&sc520_cdp_hose);
194}
195
196
197static void silence_uart(int port)
198{
199 outb(0, port+1);
200}
201
202void setup_ali_sio(int uart_primary)
203{
204 ali512x_init();
wdenk8bde7f72003-06-27 21:31:46 +0000205
wdenk2262cfe2002-11-18 00:14:45 +0000206 ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
207 ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
208 ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
209 ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
210 ali512x_set_rtc(ALI_DISABLED, 0, 0);
211 ali512x_set_kbc(ALI_ENABLED, 1, 12);
212 ali512x_set_cio(ALI_ENABLED);
wdenk8bde7f72003-06-27 21:31:46 +0000213
wdenk2262cfe2002-11-18 00:14:45 +0000214 /* IrDa pins */
215 ali512x_cio_function(12, 1, 0, 0);
216 ali512x_cio_function(13, 1, 0, 0);
wdenk8bde7f72003-06-27 21:31:46 +0000217
wdenk2262cfe2002-11-18 00:14:45 +0000218 /* SSI chip select pins */
219 ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
wdenk8bde7f72003-06-27 21:31:46 +0000220 ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
wdenk7a8e9bed2003-05-31 18:35:21 +0000221 ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
wdenk2262cfe2002-11-18 00:14:45 +0000222
223 /* Board REV pins */
224 ali512x_cio_function(20, 0, 0, 1);
225 ali512x_cio_function(21, 0, 0, 1);
226 ali512x_cio_function(22, 0, 0, 1);
wdenk8bde7f72003-06-27 21:31:46 +0000227 ali512x_cio_function(23, 0, 0, 1);
wdenk2262cfe2002-11-18 00:14:45 +0000228}
229
230
231/* set up the ISA bus timing and system address mappings */
232static void bus_init(void)
233{
234
235 /* set up the GP IO pins */
wdenk8bde7f72003-06-27 21:31:46 +0000236 write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
wdenk2262cfe2002-11-18 00:14:45 +0000237 write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
wdenk8bde7f72003-06-27 21:31:46 +0000238 write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
wdenk2262cfe2002-11-18 00:14:45 +0000239 write_mmcr_byte(SC520_CLKSEL, 0x70);
240
wdenk8bde7f72003-06-27 21:31:46 +0000241
242 write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
wdenk2262cfe2002-11-18 00:14:45 +0000243 write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
244 write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
245 write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
246 write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
wdenk8bde7f72003-06-27 21:31:46 +0000247 write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
wdenk2262cfe2002-11-18 00:14:45 +0000248 write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
249
wdenk8bde7f72003-06-27 21:31:46 +0000250 write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
wdenk2262cfe2002-11-18 00:14:45 +0000251 write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
wdenk8bde7f72003-06-27 21:31:46 +0000252 write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
253
wdenk2262cfe2002-11-18 00:14:45 +0000254 /* adjust the memory map:
255 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
256 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
wdenk8bde7f72003-06-27 21:31:46 +0000257 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
258
259
wdenk2262cfe2002-11-18 00:14:45 +0000260 /* SRAM = GPCS3 128k @ d0000-effff*/
wdenk8bde7f72003-06-27 21:31:46 +0000261 write_mmcr_long(SC520_PAR2, 0x4e00400d);
262
wdenk2262cfe2002-11-18 00:14:45 +0000263 /* IDE0 = GPCS6 1f0-1f7 */
wdenk8bde7f72003-06-27 21:31:46 +0000264 write_mmcr_long(SC520_PAR3, 0x380801f0);
wdenk2262cfe2002-11-18 00:14:45 +0000265
266 /* IDE1 = GPCS7 3f6 */
wdenk8bde7f72003-06-27 21:31:46 +0000267 write_mmcr_long(SC520_PAR4, 0x3c0003f6);
wdenk2262cfe2002-11-18 00:14:45 +0000268 /* bootcs */
wdenk8bde7f72003-06-27 21:31:46 +0000269 write_mmcr_long(SC520_PAR12, 0x8bffe800);
wdenk2262cfe2002-11-18 00:14:45 +0000270 /* romcs2 */
wdenk8bde7f72003-06-27 21:31:46 +0000271 write_mmcr_long(SC520_PAR13, 0xcbfff000);
wdenk2262cfe2002-11-18 00:14:45 +0000272 /* romcs1 */
wdenk8bde7f72003-06-27 21:31:46 +0000273 write_mmcr_long(SC520_PAR14, 0xabfff800);
wdenk2262cfe2002-11-18 00:14:45 +0000274 /* 680 LEDS */
wdenk8bde7f72003-06-27 21:31:46 +0000275 write_mmcr_long(SC520_PAR15, 0x30000640);
276
wdenk7a8e9bed2003-05-31 18:35:21 +0000277 write_mmcr_byte(SC520_ADDDECCTL, 0);
wdenk8bde7f72003-06-27 21:31:46 +0000278
279 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
wdenk2262cfe2002-11-18 00:14:45 +0000280
281 if (CFG_USE_SIO_UART) {
wdenk8bde7f72003-06-27 21:31:46 +0000282 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
wdenk2262cfe2002-11-18 00:14:45 +0000283 setup_ali_sio(1);
284 } else {
wdenk7a8e9bed2003-05-31 18:35:21 +0000285 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
wdenk2262cfe2002-11-18 00:14:45 +0000286 setup_ali_sio(0);
287 silence_uart(0x3e8);
288 silence_uart(0x2e8);
289 }
290
291}
292
wdenk7a8e9bed2003-05-31 18:35:21 +0000293/* GPCS usage
294 * GPCS0 PIO27 (NMI)
295 * GPCS1 ROMCS1
296 * GPCS2 ROMCS2
297 * GPCS3 SRAMCS PAR2
298 * GPCS4 unused PAR3
299 * GPCS5 unused PAR4
300 * GPCS6 IDE
301 * GPCS7 IDE
302 */
wdenk2262cfe2002-11-18 00:14:45 +0000303
304
wdenk7a8e9bed2003-05-31 18:35:21 +0000305/* par usage:
306 * PAR0 legacy_video
307 * PAR1 PCI ROM mapping
308 * PAR2 SRAM
309 * PAR3 IDE
310 * PAR4 IDE
311 * PAR5 legacy_video
312 * PAR6 legacy_video
313 * PAR7 legacy_video
314 * PAR8 legacy_video
315 * PAR9 legacy_video
316 * PAR10 legacy_video
317 * PAR11 ISAROM
318 * PAR12 BOOTCS
319 * PAR13 ROMCS1
320 * PAR14 ROMCS2
321 * PAR15 Port 0x680 LED display
322 */
323
wdenk8bde7f72003-06-27 21:31:46 +0000324/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000325 * This function should map a chunk of size bytes
326 * of the system address space to the ISA bus
wdenk8bde7f72003-06-27 21:31:46 +0000327 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000328 * The function will return the memory address
329 * as seen by the host (which may very will be the
330 * same as the bus address)
331 */
wdenk8bde7f72003-06-27 21:31:46 +0000332u32 isa_map_rom(u32 bus_addr, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000333{
334 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000335
336 PRINTF("isa_map_rom asked to map %d bytes at %x\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000337 size, bus_addr);
wdenk8bde7f72003-06-27 21:31:46 +0000338
wdenk7a8e9bed2003-05-31 18:35:21 +0000339 par = size;
340 if (par < 0x80000) {
341 par = 0x80000;
342 }
343 par >>= 12;
344 par--;
345 par&=0x7f;
346 par <<= 18;
347 par |= (bus_addr>>12);
348 par |= 0x50000000;
wdenk8bde7f72003-06-27 21:31:46 +0000349
wdenk7a8e9bed2003-05-31 18:35:21 +0000350 PRINTF ("setting PAR11 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000351
wdenk7a8e9bed2003-05-31 18:35:21 +0000352 /* Map rom 0x10000 with PAR1 */
353 write_mmcr_long(SC520_PAR11, par);
wdenk8bde7f72003-06-27 21:31:46 +0000354
wdenk7a8e9bed2003-05-31 18:35:21 +0000355 return bus_addr;
356}
357
358/*
359 * this function removed any mapping created
360 * with pci_get_rom_window()
361 */
362void isa_unmap_rom(u32 addr)
363{
364 PRINTF("isa_unmap_rom asked to unmap %x", addr);
365 if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
366 write_mmcr_long(SC520_PAR11, 0);
367 PRINTF(" done\n");
368 return;
369 }
370 PRINTF(" not ours\n");
371}
372
373#ifdef CONFIG_PCI
374#define PCI_ROM_TEMP_SPACE 0x10000
wdenk8bde7f72003-06-27 21:31:46 +0000375/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000376 * This function should map a chunk of size bytes
377 * of the system address space to the PCI bus,
378 * suitable to map PCI ROMS (bus address < 16M)
379 * the function will return the host memory address
380 * which should be converted into a bus address
wdenk8bde7f72003-06-27 21:31:46 +0000381 * before used to configure the PCI rom address
wdenk7a8e9bed2003-05-31 18:35:21 +0000382 * decoder
383 */
wdenk8bde7f72003-06-27 21:31:46 +0000384u32 pci_get_rom_window(struct pci_controller *hose, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000385{
386 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000387
wdenk7a8e9bed2003-05-31 18:35:21 +0000388 par = size;
389 if (par < 0x80000) {
390 par = 0x80000;
391 }
392 par >>= 16;
393 par--;
394 par&=0x7ff;
395 par <<= 14;
396 par |= (PCI_ROM_TEMP_SPACE>>16);
397 par |= 0x72000000;
wdenk8bde7f72003-06-27 21:31:46 +0000398
wdenk7a8e9bed2003-05-31 18:35:21 +0000399 PRINTF ("setting PAR1 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000400
wdenk7a8e9bed2003-05-31 18:35:21 +0000401 /* Map rom 0x10000 with PAR1 */
402 write_mmcr_long(SC520_PAR1, par);
wdenk8bde7f72003-06-27 21:31:46 +0000403
wdenk7a8e9bed2003-05-31 18:35:21 +0000404 return PCI_ROM_TEMP_SPACE;
405}
406
407/*
408 * this function removed any mapping created
409 * with pci_get_rom_window()
410 */
411void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
412{
413 PRINTF("pci_remove_rom_window: %x", addr);
414 if (addr == PCI_ROM_TEMP_SPACE) {
415 write_mmcr_long(SC520_PAR1, 0);
416 PRINTF(" done\n");
417 return;
418 }
419 PRINTF(" not ours\n");
wdenk8bde7f72003-06-27 21:31:46 +0000420
wdenk7a8e9bed2003-05-31 18:35:21 +0000421}
422
423/*
424 * This function is called in order to provide acces to the
wdenk8bde7f72003-06-27 21:31:46 +0000425 * legacy video I/O ports on the PCI bus.
426 * After this function accesses to I/O ports 0x3b0-0x3bb and
wdenk7a8e9bed2003-05-31 18:35:21 +0000427 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
wdenk8bde7f72003-06-27 21:31:46 +0000428 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000429 */
430int pci_enable_legacy_video_ports(struct pci_controller *hose)
431{
432 /* Map video memory to 0xa0000*/
433 write_mmcr_long(SC520_PAR0, 0x7200400a);
wdenk8bde7f72003-06-27 21:31:46 +0000434
wdenk7a8e9bed2003-05-31 18:35:21 +0000435 /* forward all I/O accesses to PCI */
wdenk8bde7f72003-06-27 21:31:46 +0000436 write_mmcr_byte(SC520_ADDDECCTL,
437 read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
438
439
wdenk7a8e9bed2003-05-31 18:35:21 +0000440 /* so we map away all io ports to pci (only way to access pci io
441 * below 0x400. But then we have to map back the portions that we dont
442 * use so that the generate cycles on the GPIO bus where the sio and
wdenk8bde7f72003-06-27 21:31:46 +0000443 * ISA slots are connected, this requre the use of several PAR registers
wdenk7a8e9bed2003-05-31 18:35:21 +0000444 */
wdenk8bde7f72003-06-27 21:31:46 +0000445
wdenk7a8e9bed2003-05-31 18:35:21 +0000446 /* bring 0x100 - 0x1ef back to ISA using PAR5 */
wdenk8bde7f72003-06-27 21:31:46 +0000447 write_mmcr_long(SC520_PAR5, 0x30ef0100);
448
wdenk7a8e9bed2003-05-31 18:35:21 +0000449 /* IDE use 1f0-1f7 */
wdenk8bde7f72003-06-27 21:31:46 +0000450
wdenk7a8e9bed2003-05-31 18:35:21 +0000451 /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
wdenk8bde7f72003-06-27 21:31:46 +0000452 write_mmcr_long(SC520_PAR6, 0x30ff01f8);
453
wdenk7a8e9bed2003-05-31 18:35:21 +0000454 /* com2 use 2f8-2ff */
wdenk8bde7f72003-06-27 21:31:46 +0000455
wdenk7a8e9bed2003-05-31 18:35:21 +0000456 /* bring 0x300 - 0x3af back to ISA using PAR7 */
wdenk8bde7f72003-06-27 21:31:46 +0000457 write_mmcr_long(SC520_PAR7, 0x30af0300);
458
wdenk7a8e9bed2003-05-31 18:35:21 +0000459 /* vga use 3b0-3bb */
wdenk8bde7f72003-06-27 21:31:46 +0000460
wdenk7a8e9bed2003-05-31 18:35:21 +0000461 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
wdenk8bde7f72003-06-27 21:31:46 +0000462 write_mmcr_long(SC520_PAR8, 0x300303bc);
463
wdenk7a8e9bed2003-05-31 18:35:21 +0000464 /* vga use 3c0-3df */
wdenk8bde7f72003-06-27 21:31:46 +0000465
wdenk7a8e9bed2003-05-31 18:35:21 +0000466 /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
wdenk8bde7f72003-06-27 21:31:46 +0000467 write_mmcr_long(SC520_PAR9, 0x301503e0);
468
wdenk7a8e9bed2003-05-31 18:35:21 +0000469 /* ide use 3f6 */
wdenk8bde7f72003-06-27 21:31:46 +0000470
wdenk7a8e9bed2003-05-31 18:35:21 +0000471 /* bring 0x3f7 back to ISA using PAR10 */
wdenk8bde7f72003-06-27 21:31:46 +0000472 write_mmcr_long(SC520_PAR10, 0x300003f7);
473
474 /* com1 use 3f8-3ff */
wdenk7a8e9bed2003-05-31 18:35:21 +0000475
476 return 0;
477}
478#endif
479
wdenk2262cfe2002-11-18 00:14:45 +0000480/*
481 * Miscelaneous platform dependent initialisations
482 */
483
484int board_init(void)
485{
wdenk8bde7f72003-06-27 21:31:46 +0000486 init_sc520();
wdenk2262cfe2002-11-18 00:14:45 +0000487 bus_init();
488 irq_init();
wdenk8bde7f72003-06-27 21:31:46 +0000489
wdenk2262cfe2002-11-18 00:14:45 +0000490 /* max drive current on SDRAM */
491 write_mmcr_word(SC520_DSCTL, 0x0100);
wdenk8bde7f72003-06-27 21:31:46 +0000492
wdenk2262cfe2002-11-18 00:14:45 +0000493 /* enter debug mode after next reset (only if jumper is also set) */
494 write_mmcr_byte(SC520_RESCFG, 0x08);
wdenk2262cfe2002-11-18 00:14:45 +0000495 /* configure the software timer to 33.333MHz */
496 write_mmcr_byte(SC520_SWTMRCFG, 0);
497 gd->bus_clk = 33333000;
wdenk8bde7f72003-06-27 21:31:46 +0000498
wdenk2262cfe2002-11-18 00:14:45 +0000499 return 0;
500}
501
502int dram_init(void)
503{
504 init_sc520_dram();
505 return 0;
506}
507
508void show_boot_progress(int val)
509{
510 outb(val&0xff, 0x80);
511 outb((val&0xff00)>>8, 0x680);
512}
513
514
515int last_stage_init(void)
516{
517 int minor;
518 int major;
wdenk8bde7f72003-06-27 21:31:46 +0000519
wdenk2262cfe2002-11-18 00:14:45 +0000520 major = minor = 0;
521 major |= ali512x_cio_in(23)?2:0;
522 major |= ali512x_cio_in(22)?1:0;
523 minor |= ali512x_cio_in(21)?2:0;
524 minor |= ali512x_cio_in(20)?1:0;
wdenk8bde7f72003-06-27 21:31:46 +0000525
wdenk2262cfe2002-11-18 00:14:45 +0000526 printf("AMD SC520 CDP revision %d.%d\n", major, minor);
wdenk8bde7f72003-06-27 21:31:46 +0000527
wdenkea909b72002-11-21 23:11:29 +0000528 return 0;
wdenk2262cfe2002-11-18 00:14:45 +0000529}
wdenk7a8e9bed2003-05-31 18:35:21 +0000530
531
wdenk8bde7f72003-06-27 21:31:46 +0000532void ssi_chip_select(int dev)
wdenk7a8e9bed2003-05-31 18:35:21 +0000533{
wdenk8bde7f72003-06-27 21:31:46 +0000534
wdenk7a8e9bed2003-05-31 18:35:21 +0000535 /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
536 switch (dev) {
537 case 1: /* SPI EEPROM */
538 ali512x_cio_out(16, 0);
539 break;
wdenk8bde7f72003-06-27 21:31:46 +0000540
wdenk7a8e9bed2003-05-31 18:35:21 +0000541 case 2: /* MW EEPROM */
542 ali512x_cio_out(15, 1);
543 break;
wdenk8bde7f72003-06-27 21:31:46 +0000544
545 case 3: /* AUX */
wdenk7a8e9bed2003-05-31 18:35:21 +0000546 ali512x_cio_out(14, 1);
547 break;
wdenk8bde7f72003-06-27 21:31:46 +0000548
wdenk7a8e9bed2003-05-31 18:35:21 +0000549 case 0:
550 ali512x_cio_out(16, 1);
551 ali512x_cio_out(15, 0);
552 ali512x_cio_out(14, 0);
553 break;
wdenk8bde7f72003-06-27 21:31:46 +0000554
wdenk7a8e9bed2003-05-31 18:35:21 +0000555 default:
556 printf("Illegal SSI device requested: %d\n", dev);
557 }
558}
559
wdenkbdccc4f2003-08-05 17:43:17 +0000560void spi_eeprom_probe(int x)
561{
562}
563
564int spi_eeprom_read(int x, int offset, char *buffer, int len)
565{
566 return 0;
567}
568
569int spi_eeprom_write(int x, int offset, char *buffer, int len)
570{
571 return 0;
572}
wdenk7a8e9bed2003-05-31 18:35:21 +0000573
wdenk8bde7f72003-06-27 21:31:46 +0000574void spi_init_f(void)
wdenk7a8e9bed2003-05-31 18:35:21 +0000575{
576#ifdef CONFIG_SC520_CDP_USE_SPI
wdenk8bde7f72003-06-27 21:31:46 +0000577 spi_eeprom_probe(1);
578#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000579#ifdef CONFIG_SC520_CDP_USE_MW
580 mw_eeprom_probe(2);
wdenk8bde7f72003-06-27 21:31:46 +0000581#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000582}
583
wdenk8bde7f72003-06-27 21:31:46 +0000584ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000585{
586 int offset;
587 int i;
588 ssize_t res;
wdenk8bde7f72003-06-27 21:31:46 +0000589
wdenk7a8e9bed2003-05-31 18:35:21 +0000590 offset = 0;
591 for (i=0;i<alen;i++) {
592 offset <<= 8;
593 offset |= addr[i];
594 }
wdenk8bde7f72003-06-27 21:31:46 +0000595
wdenk7a8e9bed2003-05-31 18:35:21 +0000596#ifdef CONFIG_SC520_CDP_USE_SPI
wdenk8bde7f72003-06-27 21:31:46 +0000597 res = spi_eeprom_read(1, offset, buffer, len);
598#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000599#ifdef CONFIG_SC520_CDP_USE_MW
600 res = mw_eeprom_read(2, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000601#endif
wdenkbdccc4f2003-08-05 17:43:17 +0000602#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
603 res = 0;
604#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000605 return res;
606}
607
wdenk8bde7f72003-06-27 21:31:46 +0000608ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000609{
610 int offset;
611 int i;
612 ssize_t res;
wdenk8bde7f72003-06-27 21:31:46 +0000613
wdenk7a8e9bed2003-05-31 18:35:21 +0000614 offset = 0;
615 for (i=0;i<alen;i++) {
616 offset <<= 8;
617 offset |= addr[i];
618 }
wdenk8bde7f72003-06-27 21:31:46 +0000619
wdenk7a8e9bed2003-05-31 18:35:21 +0000620#ifdef CONFIG_SC520_CDP_USE_SPI
621 res = spi_eeprom_write(1, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000622#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000623#ifdef CONFIG_SC520_CDP_USE_MW
624 res = mw_eeprom_write(2, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000625#endif
wdenkbdccc4f2003-08-05 17:43:17 +0000626#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
627 res = 0;
628#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000629 return res;
630}