blob: c4c5a2d225c4b210478157e51df626266ef5c4f9 [file] [log] [blame]
Kever Yang590dc422019-07-01 11:49:10 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd
4 */
5
Jagan Teki79030a42020-01-10 00:16:21 +05306#include "rockchip-u-boot.dtsi"
7
Kever Yangb39ab7f2019-07-09 21:58:54 +08008/ {
Johan Jonker52a0c682022-04-15 23:21:39 +02009 aliases {
10 gpio0 = &gpio0;
11 gpio1 = &gpio1;
12 gpio2 = &gpio2;
13 gpio3 = &gpio3;
14 gpio4 = &gpio4;
15 gpio5 = &gpio5;
16 gpio6 = &gpio6;
17 gpio7 = &gpio7;
18 gpio8 = &gpio8;
19 mmc0 = &emmc;
20 mmc1 = &sdmmc;
21 mmc2 = &sdio0;
22 mmc3 = &sdio1;
23 };
24
Kever Yangb39ab7f2019-07-09 21:58:54 +080025 chosen {
26 u-boot,spl-boot-order = \
27 "same-as-spl", &emmc, &sdmmc;
28 };
Johan Jonker52a0c682022-04-15 23:21:39 +020029
30 dmc: dmc@ff610000 {
31 compatible = "rockchip,rk3288-dmc", "syscon";
32 reg = <0xff610000 0x3fc
33 0xff620000 0x294
34 0xff630000 0x3fc
35 0xff640000 0x294>;
36 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
37 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
38 <&cru ARMCLK>;
39 clock-names = "pclk_ddrupctl0", "pclk_publ0",
40 "pclk_ddrupctl1", "pclk_publ1",
41 "arm_clk";
42 rockchip,cru = <&cru>;
43 rockchip,grf = <&grf>;
44 rockchip,noc = <&noc>;
45 rockchip,pmu = <&pmu>;
46 rockchip,sgrf = <&sgrf>;
47 rockchip,sram = <&ddr_sram>;
Simon Glass8c103c32023-02-13 08:56:33 -070048 bootph-all;
Johan Jonker52a0c682022-04-15 23:21:39 +020049 };
50
51 noc: syscon@ffac0000 {
52 compatible = "rockchip,rk3288-noc", "syscon";
53 reg = <0xffac0000 0x2000>;
Simon Glass8c103c32023-02-13 08:56:33 -070054 bootph-all;
Johan Jonker52a0c682022-04-15 23:21:39 +020055 };
Kever Yangb39ab7f2019-07-09 21:58:54 +080056};
57
Quentin Schulza4bb36d2022-09-02 15:10:54 +020058#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
Simon Glass9b312e22020-07-19 13:55:57 -060059&binman {
60 rom {
61 filename = "u-boot.rom";
62 size = <0x400000>;
63 pad-byte = <0xff>;
64
65 mkimage {
66 args = "-n rk3288 -T rkspi";
67 u-boot-spl {
68 };
69 };
70 u-boot-img {
71 offset = <0x20000>;
72 };
73 u-boot {
74 offset = <0x300000>;
75 };
76 fdtmap {
77 };
78 };
79};
80#endif
81
Johan Jonker52a0c682022-04-15 23:21:39 +020082&bus_intmem {
83 ddr_sram: ddr-sram@1000 {
84 compatible = "rockchip,rk3288-ddr-sram";
85 reg = <0x1000 0x4000>;
86 };
87};
88
89&cru {
Simon Glass8c103c32023-02-13 08:56:33 -070090 bootph-all;
Johan Jonker52a0c682022-04-15 23:21:39 +020091};
92
Johan Jonkerbf136762023-03-15 19:33:50 +010093&edp {
94 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
95 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
96};
97
Johan Jonker52a0c682022-04-15 23:21:39 +020098&gpio7 {
Simon Glass8c103c32023-02-13 08:56:33 -070099 bootph-all;
Johan Jonker52a0c682022-04-15 23:21:39 +0200100};
101
102&grf {
Simon Glass8c103c32023-02-13 08:56:33 -0700103 bootph-all;
Kever Yang590dc422019-07-01 11:49:10 +0800104};
105
106&pmu {
Simon Glass8c103c32023-02-13 08:56:33 -0700107 bootph-all;
Kever Yang590dc422019-07-01 11:49:10 +0800108};
109
110&sgrf {
Simon Glass8c103c32023-02-13 08:56:33 -0700111 bootph-all;
Kever Yang590dc422019-07-01 11:49:10 +0800112};
113
Johan Jonker52a0c682022-04-15 23:21:39 +0200114&uart0 {
115 clock-frequency = <24000000>;
Kever Yang590dc422019-07-01 11:49:10 +0800116};
117
Johan Jonker52a0c682022-04-15 23:21:39 +0200118&uart1 {
119 clock-frequency = <24000000>;
120};
121
122&uart2 {
123 clock-frequency = <24000000>;
124};
125
126&uart3 {
127 clock-frequency = <24000000>;
Kever Yang590dc422019-07-01 11:49:10 +0800128};
129
130&vopb {
Simon Glass8c103c32023-02-13 08:56:33 -0700131 bootph-all;
Kever Yang590dc422019-07-01 11:49:10 +0800132};
133
134&vopl {
Simon Glass8c103c32023-02-13 08:56:33 -0700135 bootph-all;
Kever Yang590dc422019-07-01 11:49:10 +0800136};