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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_CPU86 1 /* ...on a CPU86 board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000039
40/*
41 * select serial console configuration
42 *
43 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
44 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
45 * for SCC).
46 *
47 * if CONFIG_CONS_NONE is defined, then the serial console routines must
48 * defined elsewhere (for example, on the cogent platform, there are serial
49 * ports on the motherboard which are used for the serial console - see
50 * cogent/cma101/serial.[ch]).
51 */
52#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
53#define CONFIG_CONS_ON_SCC /* define if console on SCC */
54#undef CONFIG_CONS_NONE /* define if console on something else*/
55#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
56
57#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
58#define CONFIG_BAUDRATE 230400
59#else
60#define CONFIG_BAUDRATE 9600
61#endif
62
63/*
64 * select ethernet configuration
65 *
66 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
68 * for FCC)
69 *
70 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050071 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +000072 */
73#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
74#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
75#undef CONFIG_ETHER_NONE /* define if ether on something else */
76#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
77
78#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
79
80/*
81 * - Rx-CLK is CLK11
82 * - Tx-CLK is CLK12
83 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
84 * - Enable Full Duplex in FSMR
85 */
86# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
87# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
88# define CFG_CPMFCR_RAMTYPE 0
89# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
90
91#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
92
93/*
94 * - Rx-CLK is CLK13
95 * - Tx-CLK is CLK14
96 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
97 * - Enable Full Duplex in FSMR
98 */
99# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
100# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
101# define CFG_CPMFCR_RAMTYPE 0
102# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
103
104#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
105
106/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
107#define CONFIG_8260_CLKIN 64000000 /* in Hz */
108
109#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
110
wdenk0f8c9762002-08-19 11:57:05 +0000111#define CONFIG_PREBOOT \
112 "echo; " \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100113 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
wdenk0f8c9762002-08-19 11:57:05 +0000114 "echo"
115
116#undef CONFIG_BOOTARGS
117#define CONFIG_BOOTCOMMAND \
118 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100119 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
120 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk0f8c9762002-08-19 11:57:05 +0000121 "bootm"
122
123/*-----------------------------------------------------------------------
124 * I2C/EEPROM/RTC configuration
125 */
126#define CONFIG_SOFT_I2C /* Software I2C support enabled */
127
128# define CFG_I2C_SPEED 50000
129# define CFG_I2C_SLAVE 0xFE
130/*
131 * Software (bit-bang) I2C driver configuration
132 */
133#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
134#define I2C_ACTIVE (iop->pdir |= 0x00010000)
135#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
136#define I2C_READ ((iop->pdat & 0x00010000) != 0)
137#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
138 else iop->pdat &= ~0x00010000
139#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
140 else iop->pdat &= ~0x00020000
141#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
142
143#define CONFIG_RTC_PCF8563
144#define CFG_I2C_RTC_ADDR 0x51
145
146#undef CONFIG_WATCHDOG /* watchdog disabled */
147
148/*-----------------------------------------------------------------------
149 * Disk-On-Chip configuration
150 */
151
152#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
153
154#define CFG_DOC_SUPPORT_2000
155#define CFG_DOC_SUPPORT_MILLENNIUM
156
157/*-----------------------------------------------------------------------
158 * Miscellaneous configuration options
159 */
160
161#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
162#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
163
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500164/*
165 * BOOTP options
166 */
167#define CONFIG_BOOTP_SUBNETMASK
168#define CONFIG_BOOTP_GATEWAY
169#define CONFIG_BOOTP_HOSTNAME
170#define CONFIG_BOOTP_BOOTPATH
171#define CONFIG_BOOTP_BOOTFILESIZE
wdenk0f8c9762002-08-19 11:57:05 +0000172
wdenk0f8c9762002-08-19 11:57:05 +0000173
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500174/*
175 * Command line configuration.
176 */
177#include <config_cmd_default.h>
178
179#define CONFIG_CMD_BEDBUG
180#define CONFIG_CMD_DATE
181#define CONFIG_CMD_DHCP
182#define CONFIG_CMD_DOC
183#define CONFIG_CMD_EEPROM
184#define CONFIG_CMD_I2C
185#define CONFIG_CMD_NFS
186#define CONFIG_CMD_SNTP
187
wdenk0f8c9762002-08-19 11:57:05 +0000188
189/*
190 * Miscellaneous configurable options
191 */
192#define CFG_LONGHELP /* undef to save memory */
193#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500194#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000195#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
196#else
197#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
198#endif
199#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
200#define CFG_MAXARGS 16 /* max number of command args */
201#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
202
203#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
204#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
205
206#define CFG_LOAD_ADDR 0x100000 /* default load address */
207
208#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
209
210#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
211
212#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
219#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
220
221/*-----------------------------------------------------------------------
222 * Flash configuration
223 */
224
225#define CFG_BOOTROM_BASE 0xFF800000
226#define CFG_BOOTROM_SIZE 0x00080000
227#define CFG_FLASH_BASE 0xFF000000
228#define CFG_FLASH_SIZE 0x00800000
229
230/*-----------------------------------------------------------------------
231 * FLASH organization
232 */
233#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
234#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
235
236#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
237#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
238
239/*-----------------------------------------------------------------------
240 * Other areas to be mapped
241 */
242
243/* CS3: Dual ported SRAM */
244#define CFG_DPSRAM_BASE 0x40000000
245#define CFG_DPSRAM_SIZE 0x00020000
246
247/* CS4: DiskOnChip */
248#define CFG_DOC_BASE 0xF4000000
249#define CFG_DOC_SIZE 0x00100000
250
251/* CS5: FDC37C78 controller */
252#define CFG_FDC37C78_BASE 0xF1000000
253#define CFG_FDC37C78_SIZE 0x00100000
254
255/* CS6: Board configuration registers */
256#define CFG_BCRS_BASE 0xF2000000
257#define CFG_BCRS_SIZE 0x00010000
258
259/* CS7: VME Extended Access Range */
260#define CFG_VMEEAR_BASE 0x80000000
261#define CFG_VMEEAR_SIZE 0x01000000
262
263/* CS8: VME Standard Access Range */
264#define CFG_VMESAR_BASE 0xFE000000
265#define CFG_VMESAR_SIZE 0x01000000
266
267/* CS9: VME Short I/O Access Range */
268#define CFG_VMESIOAR_BASE 0xFD000000
269#define CFG_VMESIOAR_SIZE 0x01000000
270
271/*-----------------------------------------------------------------------
272 * Hard Reset Configuration Words
273 *
274 * if you change bits in the HRCW, you must also change the CFG_*
275 * defines for the various registers affected by the HRCW e.g. changing
276 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
277 */
278#if defined(CONFIG_BOOT_ROM)
279#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
280 HRCW_BPS01 | HRCW_CS10PC01)
281#else
282#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
283#endif
284
285/* no slaves so just fill with zeros */
286#define CFG_HRCW_SLAVE1 0
287#define CFG_HRCW_SLAVE2 0
288#define CFG_HRCW_SLAVE3 0
289#define CFG_HRCW_SLAVE4 0
290#define CFG_HRCW_SLAVE5 0
291#define CFG_HRCW_SLAVE6 0
292#define CFG_HRCW_SLAVE7 0
293
294/*-----------------------------------------------------------------------
295 * Internal Memory Mapped Register
296 */
297#define CFG_IMMR 0xF0000000
298
299/*-----------------------------------------------------------------------
300 * Definitions for initial stack pointer and data area (in DPRAM)
301 */
302#define CFG_INIT_RAM_ADDR CFG_IMMR
303#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
304#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
305#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
306#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
307
308/*-----------------------------------------------------------------------
309 * Start addresses for the final memory configuration
310 * (Set up by the startup code)
311 * Please note that CFG_SDRAM_BASE _must_ start at 0
312 *
313 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
314 */
315#define CFG_SDRAM_BASE 0x00000000
316#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
317#define CFG_MONITOR_BASE TEXT_BASE
318#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
319#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
320
321#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
322# define CFG_RAMBOOT
323#endif
324
325#if 0
326/* environment is in Flash */
327#define CFG_ENV_IS_IN_FLASH 1
328#ifdef CONFIG_BOOT_ROM
329# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
330# define CFG_ENV_SIZE 0x10000
331# define CFG_ENV_SECT_SIZE 0x10000
332#endif
333#else
334/* environment is in EEPROM */
335#define CFG_ENV_IS_IN_EEPROM 1
336#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
337#define CFG_I2C_EEPROM_ADDR_LEN 1
338/* mask of address bits that overflow into the "EEPROM chip address" */
339#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
340#define CFG_EEPROM_PAGE_WRITE_BITS 4
341#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk3bac3512003-03-12 10:41:04 +0000342#define CFG_ENV_OFFSET 512
343#define CFG_ENV_SIZE (2048 - 512)
wdenk0f8c9762002-08-19 11:57:05 +0000344#endif
345
346/*
347 * Internal Definitions
348 *
349 * Boot Flags
350 */
351#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
352#define BOOTFLAG_WARM 0x02 /* Software reboot */
353
354
355/*-----------------------------------------------------------------------
356 * Cache Configuration
357 */
358#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500359#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000360# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
361#endif
362
363/*-----------------------------------------------------------------------
364 * HIDx - Hardware Implementation-dependent Registers 2-11
365 *-----------------------------------------------------------------------
366 * HID0 also contains cache control - initially enable both caches and
367 * invalidate contents, then the final state leaves only the instruction
368 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
369 * but Soft reset does not.
370 *
371 * HID1 has only read-only information - nothing to set.
372 */
373#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
wdenk8bde7f72003-06-27 21:31:46 +0000374 HID0_DCI|HID0_IFEM|HID0_ABE)
wdenk0f8c9762002-08-19 11:57:05 +0000375#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
376#define CFG_HID2 0
377
378/*-----------------------------------------------------------------------
379 * RMR - Reset Mode Register 5-5
380 *-----------------------------------------------------------------------
381 * turn on Checkstop Reset Enable
382 */
383#define CFG_RMR RMR_CSRE
384
385/*-----------------------------------------------------------------------
386 * BCR - Bus Configuration 4-25
387 *-----------------------------------------------------------------------
388 */
389#define BCR_APD01 0x10000000
390#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
391
392/*-----------------------------------------------------------------------
393 * SIUMCR - SIU Module Configuration 4-31
394 *-----------------------------------------------------------------------
395 */
396#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
397 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
398
399/*-----------------------------------------------------------------------
400 * SYPCR - System Protection Control 4-35
401 * SYPCR can only be written once after reset!
402 *-----------------------------------------------------------------------
403 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
404 */
405#if defined(CONFIG_WATCHDOG)
406#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000407 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk0f8c9762002-08-19 11:57:05 +0000408#else
409#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000410 SYPCR_SWRI|SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000411#endif /* CONFIG_WATCHDOG */
412
413/*-----------------------------------------------------------------------
414 * TMCNTSC - Time Counter Status and Control 4-40
415 *-----------------------------------------------------------------------
416 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
417 * and enable Time Counter
418 */
419#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
420
421/*-----------------------------------------------------------------------
422 * PISCR - Periodic Interrupt Status and Control 4-42
423 *-----------------------------------------------------------------------
424 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
425 * Periodic timer
426 */
427#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
428
429/*-----------------------------------------------------------------------
430 * SCCR - System Clock Control 9-8
431 *-----------------------------------------------------------------------
432 * Ensure DFBRG is Divide by 16
433 */
434#define CFG_SCCR SCCR_DFBRG01
435
436/*-----------------------------------------------------------------------
437 * RCCR - RISC Controller Configuration 13-7
438 *-----------------------------------------------------------------------
439 */
440#define CFG_RCCR 0
441
442#define CFG_MIN_AM_MASK 0xC0000000
443/*-----------------------------------------------------------------------
444 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
445 *-----------------------------------------------------------------------
446 */
447#define CFG_MPTPR 0x1F00
448
449/*-----------------------------------------------------------------------
450 * PSRT - Refresh Timer Register 10-16
451 *-----------------------------------------------------------------------
452 */
453#define CFG_PSRT 0x0f
454
455/*-----------------------------------------------------------------------
456 * PSRT - SDRAM Mode Register 10-10
457 *-----------------------------------------------------------------------
458 */
459
460 /* SDRAM initialization values for 8-column chips
461 */
462#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
463 ORxS_BPD_4 |\
464 ORxS_ROWST_PBI0_A9 |\
465 ORxS_NUMR_12)
466
467#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
468 PSDMR_BSMA_A14_A16 |\
469 PSDMR_SDA10_PBI0_A10 |\
470 PSDMR_RFRC_7_CLK |\
471 PSDMR_PRETOACT_2W |\
472 PSDMR_ACTTORW_1W |\
473 PSDMR_LDOTOPRE_1C |\
474 PSDMR_WRC_1C |\
475 PSDMR_CL_2)
476
477 /* SDRAM initialization values for 9-column chips
478 */
479#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
480 ORxS_BPD_4 |\
481 ORxS_ROWST_PBI0_A7 |\
482 ORxS_NUMR_13)
483
484#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
485 PSDMR_BSMA_A13_A15 |\
486 PSDMR_SDA10_PBI0_A9 |\
487 PSDMR_RFRC_7_CLK |\
488 PSDMR_PRETOACT_2W |\
489 PSDMR_ACTTORW_1W |\
490 PSDMR_LDOTOPRE_1C |\
491 PSDMR_WRC_1C |\
492 PSDMR_CL_2)
493
494/*
495 * Init Memory Controller:
496 *
497 * Bank Bus Machine PortSz Device
498 * ---- --- ------- ------ ------
499 * 0 60x GPCM 8 bit Boot ROM
500 * 1 60x GPCM 64 bit FLASH
501 * 2 60x SDRAM 64 bit SDRAM
502 *
503 */
504
505#define CFG_MRS_OFFS 0x00000000
506
507#ifdef CONFIG_BOOT_ROM
508/* Bank 0 - Boot ROM
509 */
510#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk8bde7f72003-06-27 21:31:46 +0000511 BRx_PS_8 |\
512 BRx_MS_GPCM_P |\
513 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000514
515#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000516 ORxG_CSNT |\
517 ORxG_ACS_DIV1 |\
518 ORxG_SCY_3_CLK |\
519 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000520
521/* Bank 1 - FLASH
522 */
523#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000524 BRx_PS_64 |\
525 BRx_MS_GPCM_P |\
526 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000527
528#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000529 ORxG_CSNT |\
530 ORxG_ACS_DIV1 |\
531 ORxG_SCY_3_CLK |\
532 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000533
534#else /* CONFIG_BOOT_ROM */
535/* Bank 0 - FLASH
536 */
537#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000538 BRx_PS_64 |\
539 BRx_MS_GPCM_P |\
540 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000541
542#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000543 ORxG_CSNT |\
544 ORxG_ACS_DIV1 |\
545 ORxG_SCY_3_CLK |\
546 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000547
548/* Bank 1 - Boot ROM
549 */
550#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk8bde7f72003-06-27 21:31:46 +0000551 BRx_PS_8 |\
552 BRx_MS_GPCM_P |\
553 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000554
555#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000556 ORxG_CSNT |\
557 ORxG_ACS_DIV1 |\
558 ORxG_SCY_3_CLK |\
559 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000560
561#endif /* CONFIG_BOOT_ROM */
562
563
564/* Bank 2 - 60x bus SDRAM
565 */
566#ifndef CFG_RAMBOOT
567#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000568 BRx_PS_64 |\
569 BRx_MS_SDRAM_P |\
570 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000571
572#define CFG_OR2_PRELIM CFG_OR2_9COL
573
574#define CFG_PSDMR CFG_PSDMR_9COL
575#endif /* CFG_RAMBOOT */
576
577/* Bank 3 - Dual Ported SRAM
578 */
579#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000580 BRx_PS_16 |\
581 BRx_MS_GPCM_P |\
582 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000583
584#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000585 ORxG_CSNT |\
586 ORxG_ACS_DIV1 |\
587 ORxG_SCY_5_CLK |\
588 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000589
590/* Bank 4 - DiskOnChip
591 */
592#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000593 BRx_PS_8 |\
594 BRx_MS_GPCM_P |\
595 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000596
597#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000598 ORxG_ACS_DIV2 |\
599 ORxG_SCY_5_CLK |\
600 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000601
602/* Bank 5 - FDC37C78 controller
603 */
604#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000605 BRx_PS_8 |\
606 BRx_MS_GPCM_P |\
607 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000608
609#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000610 ORxG_ACS_DIV2 |\
611 ORxG_SCY_8_CLK |\
612 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000613
614/* Bank 6 - Board control registers
615 */
616#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000617 BRx_PS_8 |\
618 BRx_MS_GPCM_P |\
619 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000620
621#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000622 ORxG_CSNT |\
623 ORxG_SCY_5_CLK)
wdenk0f8c9762002-08-19 11:57:05 +0000624
625/* Bank 7 - VME Extended Access Range
626 */
627#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000628 BRx_PS_32 |\
629 BRx_MS_GPCM_P |\
630 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000631
632#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000633 ORxG_CSNT |\
634 ORxG_ACS_DIV1 |\
635 ORxG_SCY_5_CLK |\
636 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000637
638/* Bank 8 - VME Standard Access Range
639 */
640#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000641 BRx_PS_16 |\
642 BRx_MS_GPCM_P |\
643 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000644
645#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000646 ORxG_CSNT |\
647 ORxG_ACS_DIV1 |\
648 ORxG_SCY_5_CLK |\
649 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000650
651/* Bank 9 - VME Short I/O Access Range
652 */
653#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000654 BRx_PS_16 |\
655 BRx_MS_GPCM_P |\
656 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000657
658#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000659 ORxG_CSNT |\
660 ORxG_ACS_DIV1 |\
661 ORxG_SCY_5_CLK |\
662 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000663
664#endif /* __CONFIG_H */