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wdenk0f8c9762002-08-19 11:57:05 +00001/*
Stefan Roese8a316c92005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenk0f8c9762002-08-19 11:57:05 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denk095b8a32005-08-02 17:06:17 +020037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
39 /* ...and on a SYCAMORE board */
wdenk0f8c9762002-08-19 11:57:05 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk0f8c9762002-08-19 11:57:05 +000042
Wolfgang Denk095b8a32005-08-02 17:06:17 +020043#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk0f8c9762002-08-19 11:57:05 +000044
Wolfgang Denk095b8a32005-08-02 17:06:17 +020045#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010046 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roese8a316c92005-08-01 16:49:12 +020047 "echo"
wdenk0f8c9762002-08-19 11:57:05 +000048
Stefan Roese8a316c92005-08-01 16:49:12 +020049#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000050
Wolfgang Denk095b8a32005-08-02 17:06:17 +020051#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese8a316c92005-08-01 16:49:12 +020052 "netdev=eth0\0" \
53 "hostname=walnut\0" \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020056 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010057 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \
60 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese8a316c92005-08-01 16:49:12 +020061 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "bootm ${kernel_addr}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020063 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denk095b8a32005-08-02 17:06:17 +020066 "bootm\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020067 "rootpath=/opt/eldk/ppc_4xx\0" \
68 "bootfile=/tftpboot/walnut/uImage\0" \
69 "kernel_addr=fff80000\0" \
70 "ramdisk_addr=fff80000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +010071 "initrd_high=30000000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020072 "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
73 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
Wolfgang Denk095b8a32005-08-02 17:06:17 +020074 "cp.b 100000 fffc0000 40000;" \
Stefan Roese8a316c92005-08-01 16:49:12 +020075 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +010076 "upd=run load update\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020077 ""
78#define CONFIG_BOOTCOMMAND "run net_nfs"
wdenk0f8c9762002-08-19 11:57:05 +000079
80#if 0
Stefan Roese8a316c92005-08-01 16:49:12 +020081#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenk0f8c9762002-08-19 11:57:05 +000082#else
Stefan Roese8a316c92005-08-01 16:49:12 +020083#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk0f8c9762002-08-19 11:57:05 +000084#endif
85
Stefan Roese8a316c92005-08-01 16:49:12 +020086#define CONFIG_BAUDRATE 115200
87
wdenk0f8c9762002-08-19 11:57:05 +000088#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
90
91#define CONFIG_MII 1 /* MII PHY management */
Wolfgang Denk095b8a32005-08-02 17:06:17 +020092#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenk0f8c9762002-08-19 11:57:05 +000093
Stefan Roese4f92ed52006-08-07 14:33:32 +020094#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
95
96#define CONFIG_NETCONSOLE /* include NetConsole support */
97#define CONFIG_NET_MULTI /* needed for NetConsole */
98
wdenk0f8c9762002-08-19 11:57:05 +000099#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
100
wdenk0f8c9762002-08-19 11:57:05 +0000101
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500102/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500103 * BOOTP options
104 */
105#define CONFIG_BOOTP_BOOTFILESIZE
106#define CONFIG_BOOTP_BOOTPATH
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109
110
111/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_ASKENV
117#define CONFIG_CMD_DATE
118#define CONFIG_CMD_DHCP
119#define CONFIG_CMD_DIAG
120#define CONFIG_CMD_EEPROM
121#define CONFIG_CMD_ELF
122#define CONFIG_CMD_I2C
123#define CONFIG_CMD_IRQ
124#define CONFIG_CMD_MII
125#define CONFIG_CMD_NET
126#define CONFIG_CMD_NFS
127#define CONFIG_CMD_PCI
128#define CONFIG_CMD_PING
129#define CONFIG_CMD_REGINFO
130#define CONFIG_CMD_SDRAM
131#define CONFIG_CMD_SNTP
132
wdenk0f8c9762002-08-19 11:57:05 +0000133
134#undef CONFIG_WATCHDOG /* watchdog disabled */
135
136#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
137
138/*
139 * Miscellaneous configurable options
140 */
141#define CFG_LONGHELP /* undef to save memory */
142#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500143#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200144#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000145#else
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200146#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000147#endif
148#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
149#define CFG_MAXARGS 16 /* max number of command args */
150#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
151
152#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
153#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
154
155/*
156 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
157 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
158 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
159 * The Linux BASE_BAUD define should match this configuration.
160 * baseBaud = cpuClock/(uartDivisor*16)
161 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
162 * set Linux BASE_BAUD to 403200.
163 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200164#undef CONFIG_SERIAL_SOFTWARE_FIFO
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200165#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
166#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
167#define CFG_BASE_BAUD 691200
wdenk0f8c9762002-08-19 11:57:05 +0000168
169/* The following table includes the supported baudrates */
170#define CFG_BAUDRATE_TABLE \
171 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
172
173#define CFG_LOAD_ADDR 0x100000 /* default load address */
174#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
175
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200176#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000177
Stefan Roese4f92ed52006-08-07 14:33:32 +0200178#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200179#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200180#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese8a316c92005-08-01 16:49:12 +0200181#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
182#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
183
Stefan Roese8a316c92005-08-01 16:49:12 +0200184/*-----------------------------------------------------------------------
185 * I2C stuff
186 *-----------------------------------------------------------------------
187 */
wdenk0f8c9762002-08-19 11:57:05 +0000188#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200189#undef CONFIG_SOFT_I2C /* I2C bit-banged */
wdenk0f8c9762002-08-19 11:57:05 +0000190#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
191#define CFG_I2C_SLAVE 0x7F
192
Stefan Roese4f92ed52006-08-07 14:33:32 +0200193#define CFG_I2C_MULTI_EEPROMS
194#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
195#define CFG_I2C_EEPROM_ADDR_LEN 1
196#define CFG_EEPROM_PAGE_WRITE_ENABLE
197#define CFG_EEPROM_PAGE_WRITE_BITS 3
198#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
199
wdenk0f8c9762002-08-19 11:57:05 +0000200/*-----------------------------------------------------------------------
201 * PCI stuff
202 *-----------------------------------------------------------------------
203 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200204#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
205#define PCI_HOST_FORCE 1 /* configure as pci host */
206#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk0f8c9762002-08-19 11:57:05 +0000207
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200208#define CONFIG_PCI /* include pci support */
209#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
210#define CONFIG_PCI_PNP /* do pci plug-and-play */
211 /* resource configuration */
Stefan Roese8a316c92005-08-01 16:49:12 +0200212#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
wdenk0f8c9762002-08-19 11:57:05 +0000213
Stefan Roese8a316c92005-08-01 16:49:12 +0200214#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
215#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200216#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
217#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
218#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
219#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
220#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
221#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk0f8c9762002-08-19 11:57:05 +0000222
223/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000224 * Start addresses for the final memory configuration
225 * (Set up by the startup code)
226 * Please note that CFG_SDRAM_BASE _must_ start at 0
227 */
228#define CFG_SDRAM_BASE 0x00000000
229#define CFG_FLASH_BASE 0xFFF80000
wdenk5d232d02003-05-22 22:52:13 +0000230#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000231#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roese8a316c92005-08-01 16:49:12 +0200232#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
233
234/*
235 * Define here the location of the environment variables (FLASH or NVRAM).
236 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200237 * supported for backward compatibility.
Stefan Roese8a316c92005-08-01 16:49:12 +0200238 */
239#if 1
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200240#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +0200241#else
242#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
243#endif
wdenk0f8c9762002-08-19 11:57:05 +0000244
245/*
246 * For booting Linux, the board info and command line data
247 * have to be in the first 8 MB of memory, since this is
248 * the maximum mapped by the Linux kernel during initialization.
249 */
250#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese8a316c92005-08-01 16:49:12 +0200251
wdenk0f8c9762002-08-19 11:57:05 +0000252/*-----------------------------------------------------------------------
253 * FLASH organization
254 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200255#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
256#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200257
wdenk0f8c9762002-08-19 11:57:05 +0000258#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
259#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
260
261#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
262#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
263
Stefan Roese8a316c92005-08-01 16:49:12 +0200264#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
265
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200266#define CFG_FLASH_ADDR0 0x5555
267#define CFG_FLASH_ADDR1 0x2aaa
268#define CFG_FLASH_WORD_SIZE unsigned char
Stefan Roese8a316c92005-08-01 16:49:12 +0200269
wdenk0f8c9762002-08-19 11:57:05 +0000270#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200271#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200272#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200273#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200274
275/* Address and size of Redundant Environment Sector */
276#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
277#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
278#endif /* CFG_ENV_IS_IN_FLASH */
279
wdenk0f8c9762002-08-19 11:57:05 +0000280/*-----------------------------------------------------------------------
281 * NVRAM organization
282 */
283#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
284#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
285
286#ifdef CFG_ENV_IS_IN_NVRAM
287#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
288#define CFG_ENV_ADDR \
289 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
290#endif
Stefan Roese8a316c92005-08-01 16:49:12 +0200291
wdenk0f8c9762002-08-19 11:57:05 +0000292/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200293 * External Bus Controller (EBC) Setup
wdenk0f8c9762002-08-19 11:57:05 +0000294 */
295
Stefan Roese8a316c92005-08-01 16:49:12 +0200296/* Memory Bank 0 (Flash Bank 0) initialization */
297#define CFG_EBC_PB0AP 0x9B015480
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200298#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000299
Stefan Roese8a316c92005-08-01 16:49:12 +0200300#define CFG_EBC_PB1AP 0x02815480
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200301#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000302
Stefan Roese8a316c92005-08-01 16:49:12 +0200303#define CFG_EBC_PB2AP 0x04815A80
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200304#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese8a316c92005-08-01 16:49:12 +0200305
306#define CFG_EBC_PB3AP 0x01815280
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200307#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese8a316c92005-08-01 16:49:12 +0200308
309#define CFG_EBC_PB7AP 0x01815280
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200310#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000311
312/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200313 * External peripheral base address
314 *-----------------------------------------------------------------------
315 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200316#define CFG_KEY_REG_BASE_ADDR 0xF0100000
317#define CFG_IR_REG_BASE_ADDR 0xF0200000
318#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
Stefan Roese8a316c92005-08-01 16:49:12 +0200319
320/*-----------------------------------------------------------------------
321 * Definitions for initial stack pointer and data area
wdenk0f8c9762002-08-19 11:57:05 +0000322 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200323#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
wdenk0f8c9762002-08-19 11:57:05 +0000324
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200325#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
326#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenk0f8c9762002-08-19 11:57:05 +0000327#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
328#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200329#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000330
331/*-----------------------------------------------------------------------
332 * Definitions for Serial Presence Detect EEPROM address
333 * (to get SDRAM settings)
334 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200335#define SPD_EEPROM_ADDRESS 0x50
wdenk0f8c9762002-08-19 11:57:05 +0000336
337/*
338 * Internal Definitions
339 *
340 * Boot Flags
341 */
342#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
343#define BOOTFLAG_WARM 0x02 /* Software reboot */
344
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500345#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000346#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
347#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
348#endif
349#endif /* __CONFIG_H */