| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> |
| 4 | * |
| 5 | * X-Powers AXP221 Power Management IC driver |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| Hans de Goede | f3fba56 | 2014-11-25 16:37:52 +0100 | [diff] [blame] | 8 | /* Page 0 addresses */ |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 9 | #define AXP221_CHIP_ID 0x03 |
| 10 | #define AXP221_OUTPUT_CTRL1 0x10 |
| Hans de Goede | 50e0d5e | 2014-12-13 14:02:38 +0100 | [diff] [blame] | 11 | #define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0) |
| 12 | #define AXP221_OUTPUT_CTRL1_DCDC1_EN (1 << 1) |
| 13 | #define AXP221_OUTPUT_CTRL1_DCDC2_EN (1 << 2) |
| 14 | #define AXP221_OUTPUT_CTRL1_DCDC3_EN (1 << 3) |
| 15 | #define AXP221_OUTPUT_CTRL1_DCDC4_EN (1 << 4) |
| 16 | #define AXP221_OUTPUT_CTRL1_DCDC5_EN (1 << 5) |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 17 | #define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) |
| 18 | #define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) |
| 19 | #define AXP221_OUTPUT_CTRL2 0x12 |
| Siarhei Siamashka | 6906df1 | 2015-01-19 05:23:30 +0200 | [diff] [blame] | 20 | #define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0) |
| 21 | #define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1) |
| 22 | #define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2) |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 23 | #define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) |
| 24 | #define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) |
| 25 | #define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) |
| 26 | #define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6) |
| Hans de Goede | 50e0d5e | 2014-12-13 14:02:38 +0100 | [diff] [blame] | 27 | #define AXP221_OUTPUT_CTRL2_DCDC1SW_EN (1 << 7) |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 28 | #define AXP221_OUTPUT_CTRL3 0x13 |
| 29 | #define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7) |
| 30 | #define AXP221_DLDO1_CTRL 0x15 |
| 31 | #define AXP221_DLDO2_CTRL 0x16 |
| 32 | #define AXP221_DLDO3_CTRL 0x17 |
| 33 | #define AXP221_DLDO4_CTRL 0x18 |
| Siarhei Siamashka | 6906df1 | 2015-01-19 05:23:30 +0200 | [diff] [blame] | 34 | #define AXP221_ELDO1_CTRL 0x19 |
| 35 | #define AXP221_ELDO2_CTRL 0x1a |
| 36 | #define AXP221_ELDO3_CTRL 0x1b |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 37 | #define AXP221_DCDC1_CTRL 0x21 |
| 38 | #define AXP221_DCDC2_CTRL 0x22 |
| 39 | #define AXP221_DCDC3_CTRL 0x23 |
| 40 | #define AXP221_DCDC4_CTRL 0x24 |
| 41 | #define AXP221_DCDC5_CTRL 0x25 |
| 42 | #define AXP221_ALDO1_CTRL 0x28 |
| Hans de Goede | 5ba4719 | 2015-01-05 16:41:49 +0100 | [diff] [blame] | 43 | #define AXP221_ALDO2_CTRL 0x29 |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 44 | #define AXP221_ALDO3_CTRL 0x2a |
| Hans de Goede | fe4b71b | 2015-12-20 16:14:31 +0100 | [diff] [blame] | 45 | #define AXP221_SHUTDOWN 0x32 |
| 46 | #define AXP221_SHUTDOWN_POWEROFF (1 << 7) |
| Hans de Goede | f3fba56 | 2014-11-25 16:37:52 +0100 | [diff] [blame] | 47 | #define AXP221_PAGE 0xff |
| 48 | |
| 49 | /* Page 1 addresses */ |
| 50 | #define AXP221_SID 0x20 |
| Oliver Schinagl | 5c7f10f | 2013-07-26 12:56:58 +0200 | [diff] [blame] | 51 | |
| Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 52 | /* For axp_gpio.c */ |
| Samuel Holland | 344df3c | 2021-08-22 18:18:04 -0500 | [diff] [blame] | 53 | #ifdef CONFIG_AXP221_POWER |
| Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 54 | #define AXP_POWER_STATUS 0x00 |
| 55 | #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) |
| Chen-Yu Tsai | 81a8aa3 | 2016-03-30 00:26:56 +0800 | [diff] [blame] | 56 | #define AXP_VBUS_IPSOUT 0x30 |
| 57 | #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) |
| 58 | #define AXP_MISC_CTRL 0x8f |
| 59 | #define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) |
| Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 60 | #define AXP_GPIO0_CTRL 0x90 |
| 61 | #define AXP_GPIO1_CTRL 0x92 |
| 62 | #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ |
| 63 | #define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ |
| 64 | #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ |
| 65 | #define AXP_GPIO_STATE 0x94 |
| 66 | #define AXP_GPIO_STATE_OFFSET 0 |
| Samuel Holland | 344df3c | 2021-08-22 18:18:04 -0500 | [diff] [blame] | 67 | #endif |