blob: 1cdcd1fdb8b0e84df2c91fe7a7df84c14205e468 [file] [log] [blame]
Tom Riniba1ed5b2021-12-14 13:36:35 -05001config ARCH_MAP_SYSMEM
Tom Rini11232132022-04-06 09:21:25 -04002 depends on SANDBOX
Tom Riniba1ed5b2021-12-14 13:36:35 -05003 def_bool y
4
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +09005config CREATE_ARCH_SYMLINK
6 bool
7
Masahiro Yamada9a387122016-06-28 10:48:42 +09008config HAVE_ARCH_IOREMAP
9 bool
10
Tom Riniab92b382021-08-26 11:47:59 -040011config SYS_CACHE_SHIFT_4
12 bool
13
14config SYS_CACHE_SHIFT_5
15 bool
16
17config SYS_CACHE_SHIFT_6
18 bool
19
20config SYS_CACHE_SHIFT_7
21 bool
22
23config SYS_CACHELINE_SIZE
24 int
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
29 # Fall-back for MIPS
30 default 32 if MIPS
31
Simon Glass0b2fa982020-12-16 21:20:06 -070032config LINKER_LIST_ALIGN
33 int
34 default 32 if SANDBOX
35 default 8 if ARM64 || X86
36 default 4
37 help
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
42
Masahiro Yamada51631252014-07-30 14:08:15 +090043choice
44 prompt "Architecture select"
45 default SANDBOX
46
47config ARC
48 bool "ARC architecture"
Michal Simek5ed063d2018-07-23 15:55:13 +020049 select ARC_TIMER
50 select CLK
Michal Simek7b564322020-08-19 10:44:20 +020051 select DM
Alexey Brodkina67ef282015-02-03 13:58:20 +030052 select HAVE_PRIVATE_LIBGCC
Alexey Brodkin01496c42015-03-17 14:55:14 +030053 select SUPPORT_OF_CONTROL
Tom Riniab92b382021-08-26 11:47:59 -040054 select SYS_CACHE_SHIFT_7
Vlad Zakharov3daa7c72017-03-21 14:49:49 +030055 select TIMER
Tom Rini83505a72022-07-31 21:08:23 -040056 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
Masahiro Yamada51631252014-07-30 14:08:15 +090058
59config ARM
60 bool "ARM architecture"
Marek Behún8f969652021-05-20 13:24:22 +020061 select ARCH_SUPPORTS_LTO
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +090062 select CREATE_ARCH_SYMLINK
Masahiro Yamada64b77ed2015-07-03 16:13:09 +090063 select HAVE_PRIVATE_LIBGCC if !ARM64
Simon Glass01537232021-12-01 09:02:38 -070064 select SUPPORT_ACPI
Masahiro Yamada783e6a72014-09-22 19:59:05 +090065 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +090066
Masahiro Yamada51631252014-07-30 14:08:15 +090067config M68K
68 bool "M68000 architecture"
angelo@sysam.it6463fd82015-12-06 17:47:59 +010069 select HAVE_PRIVATE_LIBGCC
Angelo Dureghello1e483922023-02-07 23:45:03 +010070 select USE_PRIVATE_LIBGCC
Derald D. Woods405fc832018-01-22 17:17:10 -060071 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
Tom Riniab92b382021-08-26 11:47:59 -040073 select SYS_CACHE_SHIFT_4
Angelo Dureghelloabe0f872019-03-13 21:46:51 +010074 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +090075
76config MICROBLAZE
77 bool "MicroBlaze architecture"
Masahiro Yamada783e6a72014-09-22 19:59:05 +090078 select SUPPORT_OF_CONTROL
Michal Simeka36d8672022-06-24 14:16:32 +020079 imply CMD_TIMER
80 imply SPL_REGMAP if SPL
81 imply SPL_TIMER if SPL
82 imply TIMER
83 imply XILINX_TIMER
Masahiro Yamada51631252014-07-30 14:08:15 +090084
85config MIPS
86 bool "MIPS architecture"
Masahiro Yamada9a387122016-06-28 10:48:42 +090087 select HAVE_ARCH_IOREMAP
Masahiro Yamada45ccec82014-10-24 01:30:43 +090088 select HAVE_PRIVATE_LIBGCC
Daniel Schwierzeck0fc13a92015-12-19 20:20:48 +010089 select SUPPORT_OF_CONTROL
Sean Anderson1dd56db2022-04-12 10:59:04 -040090 select SPL_SEPARATE_BSS if SPL
Masahiro Yamada51631252014-07-30 14:08:15 +090091
Masahiro Yamada51631252014-07-30 14:08:15 +090092config NIOS2
93 bool "Nios II architecture"
Thomas Choubcae80e2015-10-21 21:34:57 +080094 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020095 select DM
Tom Rini448e2b62023-01-16 15:46:49 -050096 select DM_EVENT
Michal Simek5ed063d2018-07-23 15:55:13 +020097 select OF_CONTROL
98 select SUPPORT_OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +020099 imply CMD_DM
Masahiro Yamada51631252014-07-30 14:08:15 +0900100
Masahiro Yamada51631252014-07-30 14:08:15 +0900101config PPC
102 bool "PowerPC architecture"
Masahiro Yamada45ccec82014-10-24 01:30:43 +0900103 select HAVE_PRIVATE_LIBGCC
Simon Glassc1c61572015-02-07 11:51:35 -0700104 select SUPPORT_OF_CONTROL
Derald D. Woods405fc832018-01-22 17:17:10 -0600105 select SYS_BOOT_GET_CMDLINE
106 select SYS_BOOT_GET_KBD
Masahiro Yamada51631252014-07-30 14:08:15 +0900107
Rick Chen068feb92017-12-26 13:55:58 +0800108config RISCV
Bin Meng117a4332018-09-26 06:55:06 -0700109 bool "RISC-V architecture"
Anup Patel7c8d2102019-02-25 08:14:04 +0000110 select CREATE_ARCH_SYMLINK
Rick Chen068feb92017-12-26 13:55:58 +0800111 select SUPPORT_OF_CONTROL
Bin Mengbf6cc822018-09-26 06:55:19 -0700112 select OF_CONTROL
113 select DM
Tom Rini448e2b62023-01-16 15:46:49 -0500114 select DM_EVENT
Zong Li57b99002022-11-16 07:08:39 +0000115 imply SPL_SEPARATE_BSS if SPL
Bin Mengcd1f45c2018-09-26 06:55:20 -0700116 imply DM_SERIAL
Bin Mengcd1f45c2018-09-26 06:55:20 -0700117 imply DM_MMC
118 imply DM_SPI
119 imply DM_SPI_FLASH
120 imply BLK
121 imply CLK
122 imply MTD
123 imply TIMER
Bin Mengbf6cc822018-09-26 06:55:19 -0700124 imply CMD_DM
Lukas Auer8c59f202019-08-21 21:14:45 +0200125 imply SPL_DM
126 imply SPL_OF_CONTROL
127 imply SPL_LIBCOMMON_SUPPORT
128 imply SPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600129 imply SPL_SERIAL
Lukas Auer8c59f202019-08-21 21:14:45 +0200130 imply SPL_TIMER
Rick Chen068feb92017-12-26 13:55:58 +0800131
Masahiro Yamada51631252014-07-30 14:08:15 +0900132config SANDBOX
133 bool "Sandbox"
Marek Behún94bb8912021-05-20 13:24:07 +0200134 select ARCH_SUPPORTS_LTO
Tom Rinie5ec4812017-01-22 19:43:11 -0500135 select BOARD_LATE_INIT
Michael Walleefc06442020-05-22 14:07:38 +0200136 select BZIP2
Simon Glass512369a2023-10-26 14:31:34 -0400137 select CMD_POWEROFF if CMDLINE
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900138 select DM
Tom Rini448e2b62023-01-16 15:46:49 -0500139 select DM_EVENT
Andrew Scull0518e7a2022-05-30 10:00:12 +0000140 select DM_FUZZING_ENGINE
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900141 select DM_GPIO
Michal Simek5ed063d2018-07-23 15:55:13 +0200142 select DM_I2C
143 select DM_KEYBOARD
Simon Glass9a46bd32016-06-12 23:30:26 -0600144 select DM_MMC
Michal Simek5ed063d2018-07-23 15:55:13 +0200145 select DM_SERIAL
146 select DM_SPI
147 select DM_SPI_FLASH
Michael Walleefc06442020-05-22 14:07:38 +0200148 select GZIP_COMPRESSED
Tom Rini68e54042022-11-19 18:45:23 -0500149 select IO_TRACE
Tom Rinid56b4b12017-07-22 18:36:16 -0400150 select LZO
Heinrich Schuchardt1c0bc802020-03-14 12:13:40 +0100151 select OF_BOARD_SETUP
Ramon Friedbb413332019-04-27 11:15:23 +0300152 select PCI_ENDPOINT
Michal Simek5ed063d2018-07-23 15:55:13 +0200153 select SPI
154 select SUPPORT_OF_CONTROL
Simon Glass512369a2023-10-26 14:31:34 -0400155 select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
Tom Riniab92b382021-08-26 11:47:59 -0400156 select SYS_CACHE_SHIFT_4
Wasim Khan57c675d2021-03-08 16:48:16 +0100157 select IRQ
Simon Glass512369a2023-10-26 14:31:34 -0400158 select SUPPORT_EXTENSION_SCAN if CMDLINE
Simon Glasse1722fc2021-12-01 09:02:36 -0700159 select SUPPORT_ACPI
Bin Meng0f1caa92018-08-02 23:58:03 -0700160 imply BITREVERSE
Simon Glass919e7a82018-11-15 18:43:53 -0700161 select BLOBLIST
Marek Behún1b457e72021-05-20 13:24:08 +0200162 imply LTO
Michal Simek08a00cb2018-07-23 15:55:14 +0200163 imply CMD_DM
Heinrich Schuchardt6ca5ff32020-11-12 00:29:59 +0100164 imply CMD_EXCEPTION
Simon Glassded48cd2017-05-17 03:25:44 -0600165 imply CMD_GETTIME
Simon Glass551c3932017-05-17 03:25:25 -0600166 imply CMD_HASH
Simon Glass594e8d12017-05-17 03:25:34 -0600167 imply CMD_IO
Simon Glass7d0f5c12017-05-17 03:25:36 -0600168 imply CMD_IOTRACE
Simon Glassee7c0e72017-05-17 03:25:43 -0600169 imply CMD_LZMADEC
Tom Rinia4298dd2019-05-29 17:01:28 -0400170 imply CMD_SF
Michal Simek5ed063d2018-07-23 15:55:13 +0200171 imply CMD_SF_TEST
Tom Rini91d27a12017-06-02 11:03:50 -0400172 imply CRC32_VERIFY
173 imply FAT_WRITE
Rajan Vaja31b82172018-09-19 03:43:46 -0700174 imply FIRMWARE
Andrew Scull0518e7a2022-05-30 10:00:12 +0000175 imply FUZZING_ENGINE_SANDBOX
Daniel Thompson221a9492017-05-19 17:26:58 +0100176 imply HASH_VERIFY
Tom Rini91d27a12017-06-02 11:03:50 -0400177 imply LZMA
Jens Wiklanderfe39e8e2018-09-25 16:40:17 +0200178 imply TEE
Jens Wiklander0a60a812018-09-25 16:40:23 +0200179 imply AVB_VERIFY
180 imply LIBAVB
181 imply CMD_AVB
Heinrich Schuchardtd3adee12022-01-16 13:04:06 +0100182 imply PARTITION_TYPE_GUID
Igor Opaniuk7c591a82021-02-14 16:27:27 +0100183 imply SCP03
184 imply CMD_SCP03
Jens Wiklander0a60a812018-09-25 16:40:23 +0200185 imply UDP_FUNCTION_FASTBOOT
Bin Meng4f89d492018-10-15 02:21:26 -0700186 imply VIRTIO_MMIO
187 imply VIRTIO_PCI
188 imply VIRTIO_SANDBOX
189 imply VIRTIO_BLK
190 imply VIRTIO_NET
Simon Glass2a049572018-12-10 10:37:31 -0700191 imply DM_SOUND
Ramon Friedbb413332019-04-27 11:15:23 +0300192 imply PCI_SANDBOX_EP
Simon Glassc8821632019-02-16 20:24:49 -0700193 imply PCH
Alex Margineanec9594a2019-06-03 19:12:28 +0300194 imply PHYLIB
195 imply DM_MDIO
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300196 imply DM_MDIO_MUX
Simon Glass0992a902023-05-04 16:54:57 -0600197 imply ACPI
Simon Glass3b65ee32019-12-06 21:41:54 -0700198 imply ACPI_PMC
199 imply ACPI_PMC_SANDBOX
200 imply CMD_PMC
John Chau4a4830c2020-07-02 12:01:21 +0800201 imply CMD_CLONE
Simon Glassf158ba12020-11-05 10:33:38 -0700202 imply SILENT_CONSOLE
Simon Glass51bb3382020-11-05 10:33:48 -0700203 imply BOOTARGS_SUBST
Claudiu Manoilff98da02021-03-14 20:14:57 +0800204 imply PHY_FIXED
205 imply DM_DSA
Kory Maincent95300f22021-05-04 19:31:23 +0200206 imply CMD_EXTENSION
Simon Glass93e1edf2021-11-24 09:26:44 -0700207 imply KEYBOARD
Simon Glass6405ab72021-11-24 09:26:42 -0700208 imply PHYSMEM
Simon Glass437992d2021-12-01 09:02:43 -0700209 imply GENERATE_ACPI_TABLE
Philippe Reynes059df562022-03-28 22:56:53 +0200210 imply BINMAN
Alexander Gendin04291ee2023-10-09 01:24:36 +0000211 imply CMD_MBR
212 imply CMD_MMC
Simon Glass909b15c2023-10-26 14:31:33 -0400213 imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
214 imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
215 imply CMD_SYSBOOT if BOOTSTD_FULL
Masahiro Yamada51631252014-07-30 14:08:15 +0900216
217config SH
218 bool "SuperH architecture"
Masahiro Yamada45ccec82014-10-24 01:30:43 +0900219 select HAVE_PRIVATE_LIBGCC
Marek Vasut8c2c4632019-08-31 18:27:58 +0200220 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +0900221
Masahiro Yamada51631252014-07-30 14:08:15 +0900222config X86
223 bool "x86 architecture"
Simon Glass98987902019-04-25 21:58:45 -0600224 select SUPPORT_SPL
225 select SUPPORT_TPL
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +0900226 select CREATE_ARCH_SYMLINK
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900227 select DM
Bin Meng3bf9a8e2018-10-15 02:21:16 -0700228 select HAVE_ARCH_IOMAP
Michal Simek5ed063d2018-07-23 15:55:13 +0200229 select HAVE_PRIVATE_LIBGCC
230 select OF_CONTROL
Bin Meng4f0faac2017-07-30 06:23:16 -0700231 select PCI
Simon Glasse1722fc2021-12-01 09:02:36 -0700232 select SUPPORT_ACPI
Michal Simek5ed063d2018-07-23 15:55:13 +0200233 select SUPPORT_OF_CONTROL
Tom Riniab92b382021-08-26 11:47:59 -0400234 select SYS_CACHE_SHIFT_6
Bin Meng0ce9c572017-07-30 06:23:07 -0700235 select TIMER
Michal Simek5ed063d2018-07-23 15:55:13 +0200236 select USE_PRIVATE_LIBGCC
Bin Meng0ce9c572017-07-30 06:23:07 -0700237 select X86_TSC_TIMER
Wasim Khan543d0912021-03-08 16:48:15 +0100238 select IRQ
Simon Glassbcd4e6f2020-07-19 13:55:52 -0600239 imply HAS_ROM if X86_RESET_VECTOR
Bin Meng24357df2017-07-30 19:24:02 -0700240 imply BLK
Michal Simek08a00cb2018-07-23 15:55:14 +0200241 imply CMD_DM
Simon Glassfe7604a2017-05-17 03:25:21 -0600242 imply CMD_FPGA_LOADMK
Simon Glassd91a9d72017-05-17 03:25:23 -0600243 imply CMD_GETTIME
Simon Glass594e8d12017-05-17 03:25:34 -0600244 imply CMD_IO
Simon Glass1b330892017-05-17 03:25:39 -0600245 imply CMD_IRQ
Bin Mengc11b17c2017-08-16 05:46:49 -0700246 imply CMD_PCI
Tom Rinia4298dd2019-05-29 17:01:28 -0400247 imply CMD_SF
Simon Glass719d36e2017-08-04 16:34:46 -0600248 imply CMD_SF_TEST
Simon Glasse7a815f2017-08-04 16:35:03 -0600249 imply CMD_ZBOOT
Michal Simek5ed063d2018-07-23 15:55:13 +0200250 imply DM_GPIO
251 imply DM_KEYBOARD
252 imply DM_MMC
253 imply DM_RTC
254 imply DM_SCSI
255 imply DM_SERIAL
256 imply DM_SPI
257 imply DM_SPI_FLASH
258 imply DM_USB
Simon Glass91caa3b2023-08-21 21:17:01 -0600259 imply LAST_STAGE_INIT
Simon Glassb86986c2022-10-18 07:46:31 -0600260 imply VIDEO
Michal Simek5ed063d2018-07-23 15:55:13 +0200261 imply SYSRESET
Kever Yang09259fc2019-04-02 20:41:25 +0800262 imply SPL_SYSRESET
Michal Simek5ed063d2018-07-23 15:55:13 +0200263 imply SYSRESET_X86
Chris Packhamf58ad982017-08-28 20:50:46 +1200264 imply USB_ETHER_ASIX
265 imply USB_ETHER_SMSC95XX
Michal Simek5ed063d2018-07-23 15:55:13 +0200266 imply USB_HOST_ETHER
Simon Glassc8821632019-02-16 20:24:49 -0700267 imply PCH
Simon Glass6405ab72021-11-24 09:26:42 -0700268 imply PHYSMEM
Simon Glass31d52612019-05-02 10:52:24 -0600269 imply RTC_MC146818
Simon Glass0992a902023-05-04 16:54:57 -0600270 imply ACPI
Simon Glass27ba6282021-12-01 09:02:39 -0700271 imply ACPIGEN if !QEMU && !EFI_APP
Simon Glass839d66c2020-11-05 06:32:17 -0700272 imply SYSINFO if GENERATE_SMBIOS_TABLE
273 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
Simon Glassd6b318d2021-12-18 11:27:50 -0700274 imply TIMESTAMP
Masahiro Yamada51631252014-07-30 14:08:15 +0900275
Simon Glass98987902019-04-25 21:58:45 -0600276 # Thing to enable for when SPL/TPL are enabled: SPL
277 imply SPL_DM
278 imply SPL_OF_LIBFDT
Simon Glass9ca00682021-07-10 21:14:31 -0600279 imply SPL_DRIVERS_MISC
Simon Glass83061db2021-07-10 21:14:30 -0600280 imply SPL_GPIO
Simon Glasse556d3d2019-12-06 21:42:51 -0700281 imply SPL_PINCTRL
Simon Glass98987902019-04-25 21:58:45 -0600282 imply SPL_LIBCOMMON_SUPPORT
283 imply SPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600284 imply SPL_SERIAL
Simon Glass98987902019-04-25 21:58:45 -0600285 imply SPL_SPI_FLASH_SUPPORT
Simon Glassea2ca7e2021-08-08 12:20:14 -0600286 imply SPL_SPI
Simon Glass98987902019-04-25 21:58:45 -0600287 imply SPL_OF_CONTROL
288 imply SPL_TIMER
289 imply SPL_REGMAP
290 imply SPL_SYSCON
291 # TPL
292 imply TPL_DM
Simon Glass9ca00682021-07-10 21:14:31 -0600293 imply TPL_DRIVERS_MISC
Simon Glass83061db2021-07-10 21:14:30 -0600294 imply TPL_GPIO
Simon Glasse556d3d2019-12-06 21:42:51 -0700295 imply TPL_PINCTRL
Simon Glass98987902019-04-25 21:58:45 -0600296 imply TPL_LIBCOMMON_SUPPORT
297 imply TPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600298 imply TPL_SERIAL
Simon Glass98987902019-04-25 21:58:45 -0600299 imply TPL_OF_CONTROL
300 imply TPL_TIMER
301 imply TPL_REGMAP
302 imply TPL_SYSCON
303
Chris Zankelc978b522016-08-10 18:36:44 +0300304config XTENSA
305 bool "Xtensa architecture"
306 select CREATE_ARCH_SYMLINK
307 select SUPPORT_OF_CONTROL
308
Masahiro Yamada51631252014-07-30 14:08:15 +0900309endchoice
310
Masahiro Yamada3174e4e2014-09-14 03:01:48 +0900311config SYS_ARCH
312 string
313 help
314 This option should contain the architecture name to build the
315 appropriate arch/<CONFIG_SYS_ARCH> directory.
316 All the architectures should specify this option correctly.
317
318config SYS_CPU
319 string
320 help
321 This option should contain the CPU name to build the correct
322 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
323
324 This is optional. For those targets without the CPU directory,
325 leave this option empty.
326
327config SYS_SOC
328 string
329 help
330 This option should contain the SoC name to build the directory
331 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
332
333 This is optional. For those targets without the SoC directory,
334 leave this option empty.
335
336config SYS_VENDOR
337 string
338 help
339 This option should contain the vendor name of the target board.
340 If it is set and
341 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
342 directory is compiled.
343 If CONFIG_SYS_BOARD is also set, the sources under
344 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
345
346 This is optional. For those targets without the vendor directory,
347 leave this option empty.
348
349config SYS_BOARD
350 string
351 help
352 This option should contain the name of the target board.
353 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
354 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
355 whether CONFIG_SYS_VENDOR is set or not.
356
357 This is optional. For those targets without the board directory,
358 leave this option empty.
359
360config SYS_CONFIG_NAME
361 string
362 help
363 This option should contain the base name of board header file.
364 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
365 should be included from include/config.h.
366
Vignesh Raghavendraadd49672019-04-22 21:43:32 +0530367config SYS_DISABLE_DCACHE_OPS
368 bool
369 help
370 This option disables dcache flush and dcache invalidation
371 operations. For example, on coherent systems where cache
372 operatios are not required, enable this option to avoid them.
373 Note that, its up to the individual architectures to implement
374 this functionality.
375
Tom Rinibe7dbb62021-12-12 22:12:30 -0500376config SYS_IMMR
Tom Rinidd2986a2022-03-30 09:30:15 -0400377 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
Tom Rinibe7dbb62021-12-12 22:12:30 -0500378 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
379 default 0xFF000000 if MPC8xx
380 default 0xF0000000 if ARCH_MPC8313
381 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
382 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
Pali Rohár39f42fe2022-05-02 18:29:25 +0200383 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
384 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
385 ARCH_P2020
Tom Rinibe7dbb62021-12-12 22:12:30 -0500386 default SYS_CCSRBAR_DEFAULT
387 help
388 Address for the Internal Memory-Mapped Registers (IMMR) window used
389 to configure the features of many Freescale / NXP SoCs.
390
Tom Rinie52fca22022-12-02 16:42:36 -0500391config MONITOR_IS_IN_RAM
392 bool "U-Boot is loaded in to RAM by a pre-loader"
393 depends on M68K || NIOS2
394
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100395menu "Skipping low level initialization functions"
Tom Rini11232132022-04-06 09:21:25 -0400396 depends on ARM || MIPS || RISCV
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100397
398config SKIP_LOWLEVEL_INIT
399 bool "Skip calls to certain low level initialization functions"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400400 help
401 If enabled, then certain low level initializations (like setting up
402 the memory controller) are omitted and/or U-Boot does not relocate
403 itself into RAM.
404 Normally this variable MUST NOT be defined. The only exception is
405 when U-Boot is loaded (to RAM) by some other boot loader or by a
406 debugger which performs these initializations itself.
407
408config SPL_SKIP_LOWLEVEL_INIT
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100409 bool "Skip calls to certain low level initialization functions in SPL"
410 depends on SPL
Tom Rinia2ac2b92021-08-27 21:18:30 -0400411 help
412 If enabled, then certain low level initializations (like setting up
413 the memory controller) are omitted and/or U-Boot does not relocate
414 itself into RAM.
415 Normally this variable MUST NOT be defined. The only exception is
416 when U-Boot is loaded (to RAM) by some other boot loader or by a
417 debugger which performs these initializations itself.
418
419config TPL_SKIP_LOWLEVEL_INIT
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100420 bool "Skip calls to certain low level initialization functions in TPL"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400421 depends on SPL && ARM
422 help
423 If enabled, then certain low level initializations (like setting up
424 the memory controller) are omitted and/or U-Boot does not relocate
425 itself into RAM.
426 Normally this variable MUST NOT be defined. The only exception is
427 when U-Boot is loaded (to RAM) by some other boot loader or by a
428 debugger which performs these initializations itself.
429
430config SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100431 bool "Skip call to lowlevel_init during early boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400432 depends on ARM
433 help
434 This allows just the call to lowlevel_init() to be skipped. The
435 normal CP15 init (such as enabling the instruction cache) is still
436 performed.
437
438config SPL_SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100439 bool "Skip call to lowlevel_init during early SPL boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400440 depends on SPL && ARM
441 help
442 This allows just the call to lowlevel_init() to be skipped. The
443 normal CP15 init (such as enabling the instruction cache) is still
444 performed.
445
446config TPL_SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100447 bool "Skip call to lowlevel_init during early TPL boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400448 depends on TPL && ARM
449 help
450 This allows just the call to lowlevel_init() to be skipped. The
451 normal CP15 init (such as enabling the instruction cache) is still
452 performed.
453
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100454endmenu
455
Tom Rini8c778f72022-10-28 20:27:10 -0400456config SYS_HAS_NONCACHED_MEMORY
457 bool "Enable reserving a non-cached memory area for drivers"
458 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
459 help
460 This is useful for drivers that would otherwise require a lot of
461 explicit cache maintenance. For some drivers it's also impossible to
462 properly maintain the cache. For example if the regions that need to
463 be flushed are not a multiple of the cache-line size, *and* padding
464 cannot be allocated between the regions to align them (i.e. if the
465 HW requires a contiguous array of regions, and the size of each
466 region is not cache-aligned), then a flush of one region may result
467 in overwriting data that hardware has written to another region in
468 the same cache-line. This can happen for example in network drivers
469 where descriptors for buffers are typically smaller than the CPU
470 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
471
472config SYS_NONCACHED_MEMORY
473 hex "Size in bytes of the non-cached memory area"
474 depends on SYS_HAS_NONCACHED_MEMORY
475 default 0x100000
476 help
477 Size of non-cached memory area. This area of memory will be typically
478 located right below the malloc() area and mapped uncached in the MMU.
479
Masahiro Yamada51631252014-07-30 14:08:15 +0900480source "arch/arc/Kconfig"
481source "arch/arm/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900482source "arch/m68k/Kconfig"
483source "arch/microblaze/Kconfig"
484source "arch/mips/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900485source "arch/nios2/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900486source "arch/powerpc/Kconfig"
487source "arch/sandbox/Kconfig"
488source "arch/sh/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900489source "arch/x86/Kconfig"
Chris Zankelc978b522016-08-10 18:36:44 +0300490source "arch/xtensa/Kconfig"
Rick Chen068feb92017-12-26 13:55:58 +0800491source "arch/riscv/Kconfig"
Tom Rinic6c0e562022-03-23 17:19:55 -0400492
Tom Rinid622b082022-06-16 14:04:36 -0400493if ARM || M68K || PPC
494
495source "arch/Kconfig.nxp"
496
497endif
498
Tom Rinic6c0e562022-03-23 17:19:55 -0400499source "board/keymile/Kconfig"
Michal Simek89e81e62022-06-24 14:14:59 +0200500
Michal Simek10fd6d62022-06-24 14:14:59 +0200501if MIPS || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200502
503choice
504 prompt "Endianness selection"
505 help
506 Some MIPS boards can be configured for either little or big endian
507 byte order. These modes require different U-Boot images. In general there
508 is one preferred byteorder for a particular system but some systems are
509 just as commonly used in the one or the other endianness.
510
511config SYS_BIG_ENDIAN
512 bool "Big endian"
Michal Simek10fd6d62022-06-24 14:14:59 +0200513 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200514
515config SYS_LITTLE_ENDIAN
516 bool "Little endian"
Michal Simek10fd6d62022-06-24 14:14:59 +0200517 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200518
519endchoice
520
521endif