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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenov5d108ac2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020011 */
12
13#include <common.h>
Simon Glassd96c2602019-12-28 10:44:58 -070014#include <clock_legacy.h>
Simon Glass3a7d5572019-08-01 09:46:42 -060015#include <env.h>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020016#include <pci.h>
17#include <asm/processor.h>
18#include <asm/immap_85xx.h>
19#include <ioports.h>
20#include <flash.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090021#include <linux/libfdt.h>
Sergei Poselenove18575d2008-05-07 15:10:49 +020022#include <fdt_support.h>
Andy Fleminge1eb0e22008-06-10 18:49:34 -050023#include <asm/io.h>
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +020024#include <i2c.h>
25#include <mb862xx.h>
26#include <video_fb.h>
Sergei Poselenov59abd152008-06-06 15:42:41 +020027#include "upm_table.h"
Detlev Zundel3e79b582008-08-15 15:42:12 +020028
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020029DECLARE_GLOBAL_DATA_PTR;
30
31extern flash_info_t flash_info[]; /* FLASH chips info */
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +020032extern GraphicDevice mb862xx;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020033
34void local_bus_init (void);
35ulong flash_get_size (ulong base, int banknum);
36
37int checkboard (void)
38{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000040 char buf[64];
Sergei Poselenov5e1882d2008-05-27 13:47:00 +020041 int f;
Simon Glass00caae62017-08-03 12:22:12 -060042 int i = env_get_f("serial#", buf, sizeof(buf));
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000043#ifdef CONFIG_PCI
44 char *src;
45#endif
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020046
47 puts("Board: Socrates");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000048 if (i > 0) {
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020049 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000050 puts(buf);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020051 }
52 putc('\n');
53
Heiko Schocher2a51fe02019-10-16 05:55:54 +020054#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
Andy Fleminge1eb0e22008-06-10 18:49:34 -050055 /* Check the PCI_clk sel bit */
56 if (in_be32(&gur->porpllsr) & (1<<15)) {
Sergei Poselenov5e1882d2008-05-27 13:47:00 +020057 src = "SYSCLK";
58 f = CONFIG_SYS_CLK_FREQ;
59 } else {
60 src = "PCI_CLK";
61 f = CONFIG_PCI_CLK_FREQ;
62 }
63 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020064#else
65 printf ("PCI1: disabled\n");
66#endif
67
68 /*
69 * Initialize local bus.
70 */
71 local_bus_init ();
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020072 return 0;
73}
74
75int misc_init_r (void)
76{
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020077 /*
78 * Adjust flash start and offset to detected values
79 */
80 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
81 gd->bd->bi_flashoffset = 0;
82
83 /*
84 * Check if boot FLASH isn't max size
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
Becky Brucef51cdaf2010-06-17 11:37:20 -050087 set_lbc_or(0, gd->bd->bi_flashstart |
88 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
89 set_lbc_br(0, gd->bd->bi_flashstart |
90 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020091
92 /*
93 * Re-check to get correct base address
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020096 }
97
98 /*
99 * Check if only one FLASH bank is available
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
Becky Brucef51cdaf2010-06-17 11:37:20 -0500102 set_lbc_or(1, 0);
103 set_lbc_br(1, 0);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200104
105 /*
106 * Re-do flash protection upon new addresses
107 */
108 flash_protect (FLAG_PROTECT_CLEAR,
109 gd->bd->bi_flashstart, 0xffffffff,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200111
112 /* Monitor protection ON by default */
113 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
115 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200116
117 /* Environment protection ON by default */
118 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200119 CONFIG_ENV_ADDR,
120 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200122
123 /* Redundant environment protection ON by default */
124 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200125 CONFIG_ENV_ADDR_REDUND,
Wolfgang Denkdfcd7f22009-05-15 00:16:03 +0200126 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200128 }
129
Heiko Schocher2a51fe02019-10-16 05:55:54 +0200130#if defined(CONFIG_DM_PCI)
131 pci_init();
132#endif
133
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200134 return 0;
135}
136
137/*
138 * Initialize Local Bus
139 */
140void local_bus_init (void)
141{
Becky Brucef51cdaf2010-06-17 11:37:20 -0500142 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Detlev Zundel3e79b582008-08-15 15:42:12 +0200144 sys_info_t sysinfo;
145 uint clkdiv;
146 uint lbc_mhz;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 uint lcrr = CONFIG_SYS_LBC_LCRR;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200148
Detlev Zundel3e79b582008-08-15 15:42:12 +0200149 get_sys_info (&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800150 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530151 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200152
Detlev Zundel3e79b582008-08-15 15:42:12 +0200153 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
154 if (lbc_mhz >= 66)
155 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
156 else
157 lcrr |= LCRR_DBYP; /* DLL Bypass */
158
159 out_be32 (&lbc->lcrr, lcrr);
160 asm ("sync;isync;msync");
161
162 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
163 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
164 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
165 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
166
167 /* Init UPMA for FPGA access */
168 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
Simon Glass6d1fdb12019-12-28 10:44:57 -0700169 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200170
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +0200171 /* Init UPMB for Lime controller access */
172 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
Simon Glass6d1fdb12019-12-28 10:44:57 -0700173 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200174}
175
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200176#ifdef CONFIG_BOARD_EARLY_INIT_R
177int board_early_init_r (void)
178{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Detlev Zundel3e79b582008-08-15 15:42:12 +0200180
181 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
182 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
183 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
184 udelay(200);
185 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
186
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200187 return (0);
188}
189#endif /* CONFIG_BOARD_EARLY_INIT_R */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200190
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400191#ifdef CONFIG_OF_BOARD_SETUP
Simon Glasse895a4b2014-10-23 18:58:47 -0600192int ft_board_setup(void *blob, bd_t *bd)
Sergei Poselenove18575d2008-05-07 15:10:49 +0200193{
Detlev Zundel3e79b582008-08-15 15:42:12 +0200194 u32 val[12];
195 int rc, i = 0;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200196
197 ft_cpu_setup(blob, bd);
198
Detlev Zundel3e79b582008-08-15 15:42:12 +0200199 /* Fixup NOR FLASH mapping */
200 val[i++] = 0; /* chip select number */
201 val[i++] = 0; /* always 0 */
202 val[i++] = gd->bd->bi_flashstart;
203 val[i++] = gd->bd->bi_flashsize;
204
Heiko Schocher4c65a442019-10-16 05:55:51 +0200205#if defined(CONFIG_VIDEO_MB862xx)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200207 /* Fixup LIME mapping */
208 val[i++] = 2; /* chip select number */
209 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 val[i++] = CONFIG_SYS_LIME_BASE;
211 val[i++] = CONFIG_SYS_LIME_SIZE;
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200212 }
Heiko Schocher4c65a442019-10-16 05:55:51 +0200213#endif
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200214
Detlev Zundel3e79b582008-08-15 15:42:12 +0200215 /* Fixup FPGA mapping */
216 val[i++] = 3; /* chip select number */
217 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 val[i++] = CONFIG_SYS_FPGA_BASE;
219 val[i++] = CONFIG_SYS_FPGA_SIZE;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200220
221 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
Detlev Zundel3e79b582008-08-15 15:42:12 +0200222 val, i * sizeof(u32), 1);
Sergei Poselenove18575d2008-05-07 15:10:49 +0200223 if (rc)
Detlev Zundel3e79b582008-08-15 15:42:12 +0200224 printf("Unable to update localbus ranges, err=%s\n",
Sergei Poselenove18575d2008-05-07 15:10:49 +0200225 fdt_strerror(rc));
Simon Glasse895a4b2014-10-23 18:58:47 -0600226
227 return 0;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200228}
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400229#endif /* CONFIG_OF_BOARD_SETUP */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200230
Heiko Schocher39642ab2019-10-16 05:55:49 +0200231#if defined(CONFIG_OF_SEPARATE)
232void *board_fdt_blob_setup(void)
233{
234 void *fw_dtb;
235
236 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
237 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
238 printf("DTB is not passed via %x\n", (u32)fw_dtb);
239 return NULL;
240 }
241
242 return fw_dtb;
243}
244#endif
Heiko Schocher98beb602019-10-16 05:55:53 +0200245
246int get_serial_clock(void)
247{
248 return 333333330;
249}