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Stefan Roese8b7d1f02007-01-31 16:37:34 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25/*************************************************************************
26 * (c) 2005 esd gmbh Hannover
27 *
28 *
29 * from IceCube.h file
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
31 *
32 *************************************************************************/
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44#define CONFIG_ICECUBE 1 /* ... on IceCube board */
45#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
46#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#ifndef CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_TEXT_BASE 0xFFF00000
50#endif
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010053
Becky Bruce31d82672008-05-08 19:02:12 -050054#define CONFIG_HIGH_BATS 1 /* High BATs supported */
55
Stefan Roese8b7d1f02007-01-31 16:37:34 +010056/*
57 * Serial console configuration
58 */
59#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
60#if 0 /* test-only */
61#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
62#else
63#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
64#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Stefan Roese8b7d1f02007-01-31 16:37:34 +010066
Stefan Roese8b7d1f02007-01-31 16:37:34 +010067#define CONFIG_MII
68#if 0 /* test-only !!! */
69#define CONFIG_NET_MULTI 1
70#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +010072#define CONFIG_NS8382X 1
73#endif
74
Stefan Roese8b7d1f02007-01-31 16:37:34 +010075/* Partitions */
76#define CONFIG_MAC_PARTITION
77#define CONFIG_DOS_PARTITION
78
79/* USB */
80#if 0
81#define CONFIG_USB_OHCI
Stefan Roese8b7d1f02007-01-31 16:37:34 +010082#define CONFIG_USB_STORAGE
Stefan Roese8b7d1f02007-01-31 16:37:34 +010083#endif
84
Stefan Roese8b7d1f02007-01-31 16:37:34 +010085
Jon Loeligerd794cfe2007-07-04 22:31:15 -050086/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050087 * BOOTP options
88 */
89#define CONFIG_BOOTP_BOOTFILESIZE
90#define CONFIG_BOOTP_BOOTPATH
91#define CONFIG_BOOTP_GATEWAY
92#define CONFIG_BOOTP_HOSTNAME
93
94
95/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -050096 * Command line configuration.
97 */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_EEPROM
101#define CONFIG_CMD_FAT
102#define CONFIG_CMD_EXT2
103#define CONFIG_CMD_I2C
104#define CONFIG_CMD_IDE
105#define CONFIG_CMD_BSP
106#define CONFIG_CMD_ELF
107
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100108
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200109#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110# define CONFIG_SYS_LOWBOOT 1
111# define CONFIG_SYS_LOWBOOT16 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100112#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200113#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114# define CONFIG_SYS_LOWBOOT 1
115# define CONFIG_SYS_LOWBOOT08 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100116#endif
117
118/*
119 * Autobooting
120 */
121#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
122
123#define CONFIG_PREBOOT "echo;" \
124 "echo Welcome to CBX-CPU5200 (mecp5200);" \
125 "echo"
126
127#undef CONFIG_BOOTARGS
128
129#define CONFIG_EXTRA_ENV_SETTINGS \
130 "netdev=eth0\0" \
Wolfgang Denk74357112007-02-27 14:26:04 +0100131 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
132 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
133 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
134 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
135 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
136 "loadaddr=01000000\0" \
137 "serverip=192.168.2.99\0" \
138 "gatewayip=10.0.0.79\0" \
139 "user=mu\0" \
140 "target=mecp5200.esd\0" \
141 "script=mecp5200.bat\0" \
142 "image=/tftpboot/vxWorks_mecp5200\0" \
143 "ipaddr=10.0.13.196\0" \
144 "netmask=255.255.0.0\0" \
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100145 ""
146
147#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
148
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100149/*
150 * IPB Bus clocking configuration.
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100153/*
154 * I2C configuration
155 */
156#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
160#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100161
162/*
163 * EEPROM configuration
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
169#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100170/*
171 * Flash configuration
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_BASE 0xFFC00000
174#define CONFIG_SYS_FLASH_SIZE 0x00400000
175#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
176#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
177#define CONFIG_SYS_MAX_FLASH_SECT 512
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100181
182/*
183 * Environment settings
184 */
185#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200186#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_SIZE 0x10000
188#define CONFIG_ENV_SECT_SIZE 0x10000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100189#define CONFIG_ENV_OVERWRITE 1
190#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200191#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200192#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
193#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100194 /* total size of a CAT24WC32 is 8192 bytes */
195#define CONFIG_ENV_OVERWRITE 1
196#endif
197
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200198#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
200#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100201#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100203#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
205#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
206#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100207
208
209/*
210 * Memory map
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MBAR 0xF0000000
213#define CONFIG_SYS_SDRAM_BASE 0x00000000
214#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100215
216/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200218#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100219
220
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100223
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200224#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
226# define CONFIG_SYS_RAMBOOT 1
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100227#endif
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
230#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
231#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100232
233/*
234 * Ethernet configuration
235 */
236#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800237#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100238/*
Ben Warren86321fc2009-02-05 23:58:25 -0800239 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100240 */
Ben Warren86321fc2009-02-05 23:58:25 -0800241/* #define CONFIG_MPC5xxx_FEC_MII10 */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100242#define CONFIG_PHY_ADDR 0x00
243#define CONFIG_UDP_CHECKSUM 1
244
245
246/*
247 * GPIO configuration
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100250
251/*
252 * Miscellaneous configurable options
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_LONGHELP /* undef to save memory */
255#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100258#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100260#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
262#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
263#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
266#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500275#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500277#endif
278
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100279/*
280 * Various low-level settings
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
283#define CONFIG_SYS_HID0_FINAL HID0_ICE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
286#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
287#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
290#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_CS1_START 0xfd000000
293#define CONFIG_SYS_CS1_SIZE 0x00010000
294#define CONFIG_SYS_CS1_CFG 0x10101410
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_CS_BURST 0x00000000
297#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100300
301/*-----------------------------------------------------------------------
302 * USB stuff
303 *-----------------------------------------------------------------------
304 */
305#define CONFIG_USB_CLOCK 0x0001BBBB
306#define CONFIG_USB_CONFIG 0x00001000
307
308/*-----------------------------------------------------------------------
309 * IDE/ATA stuff Supports IDE harddisk
310 *-----------------------------------------------------------------------
311 */
312
313#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
314
315#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
316#undef CONFIG_IDE_LED /* LED for ide not supported */
317
318#define CONFIG_IDE_RESET /* reset for ide supported */
319#define CONFIG_IDE_PREINIT
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
322#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100327
328/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100330
331/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100333
334/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100336
Wolfgang Denk74357112007-02-27 14:26:04 +0100337/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_STRIDE 4
Stefan Roese8b7d1f02007-01-31 16:37:34 +0100339
340#endif /* __CONFIG_H */