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wdenk7ca202f2004-08-28 22:45:57 +00001/*
Detlev Zundel69235652007-04-20 12:01:47 +02002 * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
wdenk414eec32005-04-02 22:37:54 +00003 * (C) Copyright 2005
wdenk7ca202f2004-08-28 22:45:57 +00004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36#define CONFIG_MPC852T 1
37#define CONFIG_NC650 1
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200
43#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
44
45/*
46 * 10 MHz - PLL input clock
47 */
wdenkcce625e2004-09-28 19:00:19 +000048#define CONFIG_8xx_OSCLK 10000000
wdenk7ca202f2004-08-28 22:45:57 +000049
50/*
51 * 50 MHz - default CPU clock
52 */
wdenk66ca92a2004-09-28 17:59:53 +000053#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
wdenk7ca202f2004-08-28 22:45:57 +000054
55/*
56 * 15 MHz - CPU minimum clock
57 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000
wdenk7ca202f2004-08-28 22:45:57 +000059
60/*
61 * 133 MHz - CPU maximum clock
62 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
wdenk7ca202f2004-08-28 22:45:57 +000064
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_MEASURE_CPUCLK
66#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK
wdenk7ca202f2004-08-28 22:45:57 +000067
Stefan Roesef2302d42008-08-06 14:05:38 +020068#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
dzu@denx.dea367d422006-04-19 11:52:46 +020069#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +020070#define CONFIG_AUTOBOOT_PROMPT \
71 "\nEnter password - autoboot in %d seconds...\n", bootdelay
dzu@denx.dea367d422006-04-19 11:52:46 +020072#define CONFIG_AUTOBOOT_DELAY_STR "ids"
73#define CONFIG_BOOT_RETRY_TIME 900
74#define CONFIG_BOOT_RETRY_MIN 30
wdenk7ca202f2004-08-28 22:45:57 +000075
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010076#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk7ca202f2004-08-28 22:45:57 +000077
78#undef CONFIG_BOOTARGS
79#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020080 "bootp;" \
81 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
82 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk7ca202f2004-08-28 22:45:57 +000083 "bootm"
84
Wolfgang Denk53677ef2008-05-20 16:00:29 +020085#define CONFIG_WATCHDOG /* watchdog enabled */
wdenk7ca202f2004-08-28 22:45:57 +000086
87#undef CONFIG_STATUS_LED /* Status LED disabled */
88
Jon Loeliger7be044e2007-07-09 21:24:19 -050089/*
90 * BOOTP options
91 */
92#define CONFIG_BOOTP_SUBNETMASK
93#define CONFIG_BOOTP_GATEWAY
94#define CONFIG_BOOTP_HOSTNAME
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_BOOTFILESIZE
97
wdenk7ca202f2004-08-28 22:45:57 +000098
99#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
100#define FEC_ENET
101#define CONFIG_MII
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DISCOVER_PHY 1
wdenk7ca202f2004-08-28 22:45:57 +0000103
104
105/* enable I2C and select the hardware/software driver */
106#undef CONFIG_HARD_I2C /* I2C with hardware support */
107#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
109#define CONFIG_SYS_I2C_SLAVE 0x7f
wdenk7ca202f2004-08-28 22:45:57 +0000110
111/*
112 * Software (bit-bang) I2C driver configuration
113 */
dzu@denx.dea367d422006-04-19 11:52:46 +0200114#if defined(CONFIG_IDS852_REV1)
115
wdenk4cfaf552004-10-11 23:03:10 +0000116#define SCL 0x1000 /* PA 3 */
117#define SDA 0x2000 /* PA 2 */
wdenk7ca202f2004-08-28 22:45:57 +0000118
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200119#define __I2C_DIR immr->im_ioport.iop_padir
120#define __I2C_DAT immr->im_ioport.iop_padat
121#define __I2C_PAR immr->im_ioport.iop_papar
dzu@denx.dea367d422006-04-19 11:52:46 +0200122
123#elif defined(CONFIG_IDS852_REV2)
124
125#define SCL 0x0002 /* PB 30 */
126#define SDA 0x0001 /* PB 31 */
127
128#define __I2C_PAR immr->im_cpm.cp_pbpar
129#define __I2C_DIR immr->im_cpm.cp_pbdir
130#define __I2C_DAT immr->im_cpm.cp_pbdat
131
132#endif
133
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200134#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
135 __I2C_DIR |= (SDA|SCL); }
136#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
137#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
138#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
139#define I2C_DELAY { udelay(5); }
140#define I2C_ACTIVE { __I2C_DIR |= SDA; }
141#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenk7ca202f2004-08-28 22:45:57 +0000142
wdenk4cfaf552004-10-11 23:03:10 +0000143#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk7ca202f2004-08-28 22:45:57 +0000145
wdenk7ca202f2004-08-28 22:45:57 +0000146
Jon Loeligere18a1062007-07-08 14:21:43 -0500147/*
148 * Command line configuration.
149 */
150#include <config_cmd_default.h>
151
152#define CONFIG_CMD_ASKENV
153#define CONFIG_CMD_DATE
154#define CONFIG_CMD_DHCP
155#define CONFIG_CMD_I2C
156#define CONFIG_CMD_NAND
157#define CONFIG_CMD_JFFS2
158#define CONFIG_CMD_NFS
159#define CONFIG_CMD_SNTP
160
wdenk7ca202f2004-08-28 22:45:57 +0000161
162/*
163 * Miscellaneous configurable options
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LONGHELP /* undef to save memory */
166#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere18a1062007-07-08 14:21:43 -0500167#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7ca202f2004-08-28 22:45:57 +0000169#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7ca202f2004-08-28 22:45:57 +0000171#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
173#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7ca202f2004-08-28 22:45:57 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
177#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
wdenk7ca202f2004-08-28 22:45:57 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_LOAD_ADDR 0x00100000
wdenk7ca202f2004-08-28 22:45:57 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk7ca202f2004-08-28 22:45:57 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk7ca202f2004-08-28 22:45:57 +0000184
185/*
186 * Low Level Configuration Settings
187 * (address mappings, register initial values, etc.)
188 * You should know what you are doing if you make changes here.
189 */
190/*-----------------------------------------------------------------------
191 * Internal Memory Mapped Register
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_IMMR 0xF0000000
194#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
wdenk7ca202f2004-08-28 22:45:57 +0000195
196/*-----------------------------------------------------------------------
197 * Definitions for initial stack pointer and data area (in DPRAM)
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
200#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
201#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
202#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
203#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7ca202f2004-08-28 22:45:57 +0000204
205/*-----------------------------------------------------------------------
206 * Start addresses for the final memory configuration
207 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7ca202f2004-08-28 22:45:57 +0000209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_SDRAM_BASE 0x00000000
211#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk7ca202f2004-08-28 22:45:57 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk7ca202f2004-08-28 22:45:57 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
216#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
217#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenk7ca202f2004-08-28 22:45:57 +0000218
219/*
220 * For booting Linux, the board info and command line data
221 * have to be in the first 8 MB of memory, since this is
222 * the maximum mapped by the Linux kernel during initialization.
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7ca202f2004-08-28 22:45:57 +0000225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
wdenk7ca202f2004-08-28 22:45:57 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
232#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk7ca202f2004-08-28 22:45:57 +0000233
234
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200235#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200236#define CONFIG_ENV_OFFSET 0x00740000
wdenk7ca202f2004-08-28 22:45:57 +0000237
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200238#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
239#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
wdenk7ca202f2004-08-28 22:45:57 +0000240
241/*-----------------------------------------------------------------------
242 * Cache Configuration
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500245#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk7ca202f2004-08-28 22:45:57 +0000247#endif
248
wdenk4cfaf552004-10-11 23:03:10 +0000249/*
250 * NAND flash support
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_MAX_NAND_DEVICE 1
wdenk4cfaf552004-10-11 23:03:10 +0000253
wdenk7ca202f2004-08-28 22:45:57 +0000254/*-----------------------------------------------------------------------
255 * SYPCR - System Protection Control 11-9
256 * SYPCR can only be written once after reset!
257 *-----------------------------------------------------------------------
258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
259 */
260#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk7ca202f2004-08-28 22:45:57 +0000262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
263#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk7ca202f2004-08-28 22:45:57 +0000265#endif
266
267/*-----------------------------------------------------------------------
268 * SIUMCR - SIU Module Configuration 11-6
269 *-----------------------------------------------------------------------
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk7ca202f2004-08-28 22:45:57 +0000272
273/*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk7ca202f2004-08-28 22:45:57 +0000279
280/*-----------------------------------------------------------------------
281 * PISCR - Periodic Interrupt Status and Control 11-31
282 *-----------------------------------------------------------------------
283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk7ca202f2004-08-28 22:45:57 +0000286
287/*-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
292 */
293#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
wdenk7ca202f2004-08-28 22:45:57 +0000295 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
296 SCCR_DFLCD000 | SCCR_DFALCD00)
297
298 /*-----------------------------------------------------------------------
299 *
300 *-----------------------------------------------------------------------
301 *
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_DER 0
wdenk7ca202f2004-08-28 22:45:57 +0000304
305/*
306 * Init Memory Controller:
307 *
308 * BR0 and OR0 (FLASH)
309 */
310
311#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
314#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk7ca202f2004-08-28 22:45:57 +0000315
316/* FLASH timing: Default value of OR0 after reset */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
wdenk7ca202f2004-08-28 22:45:57 +0000318 OR_SCY_15_CLK | OR_TRLX)
319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
321#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
322#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
wdenk7ca202f2004-08-28 22:45:57 +0000323
324/*
dzu@denx.dea367d422006-04-19 11:52:46 +0200325 * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
326 * rev2 only uses the chipselect
wdenk4cfaf552004-10-11 23:03:10 +0000327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_NAND_BASE 0x50000000
329#define CONFIG_SYS_NAND_SIZE 0x04000000
wdenk4cfaf552004-10-11 23:03:10 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
wdenk4cfaf552004-10-11 23:03:10 +0000332 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
335#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
wdenk4cfaf552004-10-11 23:03:10 +0000336
337/*
wdenk7ca202f2004-08-28 22:45:57 +0000338 * BR3 and OR3 (SDRAM)
339 */
340#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
341#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
342
343 /*
344 * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk7ca202f2004-08-28 22:45:57 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
349#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenk7ca202f2004-08-28 22:45:57 +0000350
351/*
dzu@denx.dea367d422006-04-19 11:52:46 +0200352 * BR4 and OR4 (CPLD)
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */
355#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */
dzu@denx.dea367d422006-04-19 11:52:46 +0200356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
dzu@denx.dea367d422006-04-19 11:52:46 +0200358 OR_SCY_1_CLK)
359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
361#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
dzu@denx.dea367d422006-04-19 11:52:46 +0200362
363/*
wdenkcacfab52004-11-17 20:44:20 +0000364 * BR5 and OR5 (SRAM)
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_SRAM_BASE 0x60000000
367#define CONFIG_SYS_SRAM_SIZE 0x00080000
wdenkcacfab52004-11-17 20:44:20 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
wdenkcacfab52004-11-17 20:44:20 +0000370 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
373#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
wdenkcacfab52004-11-17 20:44:20 +0000374
dzu@denx.dea367d422006-04-19 11:52:46 +0200375#if defined(CONFIG_CP850)
376/*
377 * BR6 and OR6 (DPRAM) - only on CP850
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR6_PRELIM 0xffff8170
380#define CONFIG_SYS_BR6_PRELIM 0xa0000401
dzu@denx.dea367d422006-04-19 11:52:46 +0200381#define DPRAM_BASE_ADDR 0xa0000000
382
383#define CONFIG_MISC_INIT_R 1
384#endif
wdenkcacfab52004-11-17 20:44:20 +0000385
wdenkcacfab52004-11-17 20:44:20 +0000386/*
wdenk7ca202f2004-08-28 22:45:57 +0000387 * 4096 Rows from SDRAM example configuration
388 * 1000 factor s -> ms
389 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
390 * 4 Number of refresh cycles per period
391 * 64 Refresh cycle in ms per number of rows
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenk7ca202f2004-08-28 22:45:57 +0000394
395/*
396 * Memory Periodic Timer Prescaler
397 */
398
399/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_MAMR_PTA 39
wdenk7ca202f2004-08-28 22:45:57 +0000401
402/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
404#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk7ca202f2004-08-28 22:45:57 +0000405
406/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
408#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk7ca202f2004-08-28 22:45:57 +0000409
410/*
411 * MAMR settings for SDRAM
412 */
413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk7ca202f2004-08-28 22:45:57 +0000415 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
416 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk7ca202f2004-08-28 22:45:57 +0000418 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
419 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
420
421/*
wdenkc3fafec2005-03-14 23:01:03 +0000422 * MBMR settings for NAND flash
423 */
424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
wdenkc3fafec2005-03-14 23:01:03 +0000426
427/*
wdenk7ca202f2004-08-28 22:45:57 +0000428 * Internal Definitions
429 *
430 * Boot Flags
431 */
432#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
433#define BOOTFLAG_WARM 0x02 /* Software reboot */
434
wdenk07cc0992005-05-05 00:04:14 +0000435#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk07cc0992005-05-05 00:04:14 +0000436#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
wdenk7ca202f2004-08-28 22:45:57 +0000437
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200438/*
439 * JFFS2 partitions
440 */
441
442/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100443#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200444#define CONFIG_JFFS2_DEV "nand0"
445#define CONFIG_JFFS2_PART_SIZE 0x00400000
446#define CONFIG_JFFS2_PART_OFFSET 0x00000000
447
448/* mtdparts command line support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100449#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200450#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
451
452#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
dzu@denx.dea367d422006-04-19 11:52:46 +0200453 "4m(cramfs1),1m(cramfs2)," \
454 "256k(u-boot),128k(env);" \
455 "nc650-nand:4m(jffs1),28m(jffs2)"
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200456
wdenk7ca202f2004-08-28 22:45:57 +0000457#endif /* __CONFIG_H */