| Alex Marginean | a7fdac7 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * NXP LS1028A-QDS device tree fragment for RCW 7xx7 |
| 4 | * |
| Vladimir Oltean | 66fd01f | 2021-09-17 14:27:13 +0300 | [diff] [blame] | 5 | * Copyright 2019-2021 NXP |
| Alex Marginean | a7fdac7 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | &slot1 { |
| 9 | #include "fsl-sch-30841.dtsi" |
| 10 | }; |
| 11 | |
| Michael Walle | c816dd0 | 2021-10-13 18:14:15 +0200 | [diff] [blame] | 12 | &enetc_port2 { |
| Vladimir Oltean | 39dca76 | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 13 | status = "okay"; |
| 14 | }; |
| 15 | |
| Alex Marginean | a7fdac7 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 16 | &mscc_felix { |
| 17 | status = "okay"; |
| 18 | }; |
| 19 | |
| 20 | &mscc_felix_port0 { |
| 21 | status = "okay"; |
| Vladimir Oltean | 7c2d5d1 | 2021-09-18 15:32:35 +0300 | [diff] [blame] | 22 | phy-mode = "2500base-x"; |
| Michael Walle | fb19c6b | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 23 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; |
| Alex Marginean | a7fdac7 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | &mscc_felix_port3 { |
| 27 | status = "okay"; |
| Vladimir Oltean | 7c2d5d1 | 2021-09-18 15:32:35 +0300 | [diff] [blame] | 28 | phy-mode = "2500base-x"; |
| Michael Walle | fb19c6b | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 29 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; |
| Alex Marginean | a7fdac7 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 30 | }; |
| Vladimir Oltean | 39dca76 | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 31 | |
| 32 | &mscc_felix_port4 { |
| Michael Walle | c816dd0 | 2021-10-13 18:14:15 +0200 | [diff] [blame] | 33 | ethernet = <&enetc_port2>; |
| Vladimir Oltean | 39dca76 | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 34 | status = "okay"; |
| 35 | }; |