blob: e843a5648e8ec5c22639b050f0810e1810ee2405 [file] [log] [blame]
Peng Fan9b15ce92019-08-27 06:26:08 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marek Vasut77cfd0d2020-04-29 15:04:24 +02006/ {
7 wdt-reboot {
8 compatible = "wdt-reboot";
9 wdt = <&wdog1>;
10 u-boot,dm-spl;
11 };
12};
13
Peng Fan387c4492019-10-16 10:24:30 +000014&{/soc@0} {
Peng Fan9b15ce92019-08-27 06:26:08 +000015 u-boot,dm-pre-reloc;
16 u-boot,dm-spl;
17};
18
19&clk {
20 u-boot,dm-spl;
21 u-boot,dm-pre-reloc;
Peng Fan98bcf9a2019-10-22 03:29:54 +000022 /delete-property/ assigned-clocks;
23 /delete-property/ assigned-clock-parents;
24 /delete-property/ assigned-clock-rates;
Peng Fan9b15ce92019-08-27 06:26:08 +000025};
26
27&osc_24m {
28 u-boot,dm-spl;
29 u-boot,dm-pre-reloc;
30};
31
32&aips1 {
33 u-boot,dm-spl;
34 u-boot,dm-pre-reloc;
35};
36
37&aips2 {
38 u-boot,dm-spl;
39};
40
41&aips3 {
42 u-boot,dm-spl;
43};
44
45&iomuxc {
46 u-boot,dm-spl;
47};
48
Andrey Zhizhikin247bbeb2020-12-05 17:29:17 +000049&reg_usdhc2_vmmc {
50 u-boot,off-on-delay-us = <20000>;
51};
52
Peng Fan9b15ce92019-08-27 06:26:08 +000053&pinctrl_reg_usdhc2_vmmc {
54 u-boot,dm-spl;
55};
56
57&pinctrl_uart2 {
58 u-boot,dm-spl;
59};
60
61&pinctrl_usdhc2_gpio {
62 u-boot,dm-spl;
63};
64
65&pinctrl_usdhc2 {
66 u-boot,dm-spl;
67};
68
69&pinctrl_usdhc3 {
70 u-boot,dm-spl;
71};
72
73&gpio1 {
74 u-boot,dm-spl;
75};
76
77&gpio2 {
78 u-boot,dm-spl;
79};
80
81&gpio3 {
82 u-boot,dm-spl;
83};
84
85&gpio4 {
86 u-boot,dm-spl;
87};
88
89&gpio5 {
90 u-boot,dm-spl;
91};
92
93&uart2 {
94 u-boot,dm-spl;
95};
96
97&usdhc1 {
98 u-boot,dm-spl;
99};
100
101&usdhc2 {
102 u-boot,dm-spl;
Andrey Zhizhikin50b1a692020-12-05 17:29:18 +0000103 sd-uhs-sdr104;
104 sd-uhs-ddr50;
Peng Fan9b15ce92019-08-27 06:26:08 +0000105};
106
107&usdhc3 {
108 u-boot,dm-spl;
Andrey Zhizhikin50b1a692020-12-05 17:29:18 +0000109 mmc-hs400-1_8v;
110 mmc-hs400-enhanced-strobe;
Peng Fan9b15ce92019-08-27 06:26:08 +0000111};
Peng Fan8c61eba2019-10-16 10:24:42 +0000112
113&i2c1 {
114 u-boot,dm-spl;
115};
116
117&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
118 u-boot,dm-spl;
119};
120
121&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
122 u-boot,dm-spl;
123};
124
125&pinctrl_i2c1 {
126 u-boot,dm-spl;
127};
128
129&pinctrl_pmic {
130 u-boot,dm-spl;
131};
Peng Fanbdcf3a82019-10-22 03:30:04 +0000132
133&fec1 {
134 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
135};
Marek Vasut77cfd0d2020-04-29 15:04:24 +0200136
137&wdog1 {
138 u-boot,dm-spl;
139};