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Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05001/*
Li Yang28a096e2010-12-30 11:17:44 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * p2020ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Galaebf9d522010-05-21 03:02:16 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Galaa0f9e0e2009-09-10 16:26:37 -050033#define CONFIG_PHYS_64BIT
34#endif
35
Jerry Huang1ac63e42011-01-24 17:09:54 +000036#ifdef CONFIG_SDCARD
37#define CONFIG_SYS_RAMBOOT
38#define CONFIG_SYS_EXTRA_ENV_RELOC
39#define CONFIG_SYS_TEXT_BASE 0xf8f80000
40#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
41#endif
42
Jerry Huang21dd9af2011-01-24 17:09:56 +000043#ifdef CONFIG_SPIFLASH
44#define CONFIG_SYS_RAMBOOT
45#define CONFIG_SYS_EXTRA_ENV_RELOC
46#define CONFIG_SYS_TEXT_BASE 0xf8f80000
47#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
48#endif
49
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050050/* High Level Configuration Options */
51#define CONFIG_BOOKE 1 /* BOOKE */
52#define CONFIG_E500 1 /* BOOKE e500 family */
53#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
54#define CONFIG_P2020 1
55#define CONFIG_P2020DS 1
56#define CONFIG_MP 1 /* support multiple processors */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050057
Wolfgang Denk2ae18242010-10-06 09:05:45 +020058#ifndef CONFIG_SYS_TEXT_BASE
59#define CONFIG_SYS_TEXT_BASE 0xeff80000
60#endif
61
Kumar Gala7a577fd2011-01-12 02:48:53 -060062#ifndef CONFIG_RESET_VECTOR_ADDRESS
63#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
64#endif
65
Li Yang28a096e2010-12-30 11:17:44 -060066#define CONFIG_SYS_SRIO
67#define CONFIG_SRIO1 /* SRIO port 1 */
68#define CONFIG_SRIO2 /* SRIO port 2 */
69
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050070#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
71#define CONFIG_PCI 1 /* Enable PCI/PCIE */
72#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
73#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
74#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
75#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
76#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
77#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
78
79#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zang29c35182009-06-30 13:56:23 +080080#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050081
82#define CONFIG_TSEC_ENET /* tsec ethernet support */
83#define CONFIG_ENV_OVERWRITE
84
Kumar Galaebf9d522010-05-21 03:02:16 -050085#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
86#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050087#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050088
89/*
90 * These can be toggled for performance analysis, otherwise use default.
91 */
92#define CONFIG_L2_CACHE /* toggle L2 cache */
93#define CONFIG_BTB /* toggle branch predition */
94
Jerry Huang9c4d8762011-01-24 17:09:53 +000095#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
96
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050097#define CONFIG_ENABLE_36BIT_PHYS 1
98
99#ifdef CONFIG_PHYS_64BIT
100#define CONFIG_ADDR_MAP 1
101#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
102#endif
103
York Sun84bc0032010-09-28 15:20:37 -0700104#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
105#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
106#define CONFIG_SYS_MEMTEST_END 0x00400000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500107#define CONFIG_PANIC_HANG /* do not reset board on panic */
108
109/*
Jerry Huang1ac63e42011-01-24 17:09:54 +0000110 * Config the L2 Cache
111 */
112#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
113#ifdef CONFIG_PHYS_64BIT
114#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
115#else
116#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
117#endif
118#define CONFIG_SYS_L2_SIZE (512 << 10)
119#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
120
121/*
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500122 * Base addresses -- Note these are effective addresses where the
123 * actual resources get mapped (not physical addresses)
124 */
125#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
126#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
127#ifdef CONFIG_PHYS_64BIT
128#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
129#else
130#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
131#endif
132#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
133
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500134/* DDR Setup */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500135#define CONFIG_VERY_BIG_RAM
Wolfgang Denkd24f2d32010-10-04 19:58:00 +0200136#ifdef CONFIG_DDR2
york394c46c2010-07-02 22:25:58 +0000137#define CONFIG_FSL_DDR2
138#else
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500139#define CONFIG_FSL_DDR3 1
york394c46c2010-07-02 22:25:58 +0000140#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500141#undef CONFIG_FSL_DDR_INTERACTIVE
142
Wolfgang Denk8e5e9b92009-07-07 22:35:02 +0200143/* ECC will be enabled based on perf_mode environment variable */
144/* #define CONFIG_DDR_ECC */
145
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500146#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
148
149#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
150#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
151
152#define CONFIG_NUM_DDR_CONTROLLERS 1
153#define CONFIG_DIMM_SLOTS_PER_CTLR 1
154#define CONFIG_CHIP_SELECTS_PER_CTRL 2
155
156/* I2C addresses of SPD EEPROMs */
york394c46c2010-07-02 22:25:58 +0000157#define CONFIG_DDR_SPD
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500158#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
Kumar Galac39f44d2011-01-31 22:18:47 -0600159#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500160
161/* These are used when DDR doesn't use SPD. */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500162#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
163
164/* Default settings for "stable" mode */
165#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
166#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
167#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
168#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
169#define CONFIG_SYS_DDR_TIMING_3 0x00020000
170#define CONFIG_SYS_DDR_TIMING_0 0x00330804
171#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
172#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
173#define CONFIG_SYS_DDR_MODE_1 0x00421422
174#define CONFIG_SYS_DDR_MODE_2 0x00000000
175#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
176#define CONFIG_SYS_DDR_INTERVAL 0x61800100
177#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
178#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
179#define CONFIG_SYS_DDR_TIMING_4 0x00220001
180#define CONFIG_SYS_DDR_TIMING_5 0x03402400
181#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
182#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
183#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
184#define CONFIG_SYS_DDR_CONTROL2 0x24400011
185#define CONFIG_SYS_DDR_CDR1 0x00040000
186#define CONFIG_SYS_DDR_CDR2 0x00000000
187
188#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
189#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
190#define CONFIG_SYS_DDR_SBE 0x00010000
191
192/* Settings that differ for "performance" mode */
193#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
194#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
195#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
196#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
197#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
198#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
199
200/*
201 * The following set of values were tested for DDR2
202 * with a DDR3 to DDR2 interposer
203 *
204#define CONFIG_SYS_DDR_TIMING_3 0x00000000
205#define CONFIG_SYS_DDR_TIMING_0 0x00260802
206#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
207#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
208#define CONFIG_SYS_DDR_MODE_1 0x00480432
209#define CONFIG_SYS_DDR_MODE_2 0x00000000
210#define CONFIG_SYS_DDR_INTERVAL 0x06180100
211#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
212#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
213#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
214#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
215#define CONFIG_SYS_DDR_CONTROL 0xC3008000
216#define CONFIG_SYS_DDR_CONTROL2 0x04400010
217 *
218 */
219
220#undef CONFIG_CLOCKS_IN_MHZ
221
222/*
223 * Memory map
224 *
225 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
226 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
227 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
228 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
229 *
230 * Localbus cacheable (TBD)
231 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
232 *
233 * Localbus non-cacheable
234 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
235 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
236 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
237 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
238 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
239 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
240 */
241
242/*
243 * Local Bus Definitions
244 */
245#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
246#ifdef CONFIG_PHYS_64BIT
247#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
248#else
249#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
250#endif
251
252#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
253#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
254
255#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
256#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
257
258#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
259#define CONFIG_SYS_FLASH_QUIET_TEST
260#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261
262#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
263#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
264#undef CONFIG_SYS_FLASH_CHECKSUM
265#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
267
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500269
270#define CONFIG_FLASH_CFI_DRIVER
271#define CONFIG_SYS_FLASH_CFI
272#define CONFIG_SYS_FLASH_EMPTY_INFO
273#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
274
275#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
276
york394c46c2010-07-02 22:25:58 +0000277#define CONFIG_HWCONFIG /* enable hwconfig */
Timur Tabi5a469602010-04-01 10:49:42 -0500278#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
279
280#ifdef CONFIG_FSL_NGPIXIS
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500281#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
282#ifdef CONFIG_PHYS_64BIT
283#define PIXIS_BASE_PHYS 0xfffdf0000ull
284#else
285#define PIXIS_BASE_PHYS PIXIS_BASE
286#endif
287
288#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
289#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
290
Timur Tabi5a469602010-04-01 10:49:42 -0500291#define PIXIS_LBMAP_SWITCH 7
292#define PIXIS_LBMAP_MASK 0xf0
293#define PIXIS_LBMAP_SHIFT 4
294#define PIXIS_LBMAP_ALTBANK 0x20
295#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500296
297#define CONFIG_SYS_INIT_RAM_LOCK 1
298#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
yorkd51cc7a2010-07-02 22:26:03 +0000299#ifdef CONFIG_PHYS_64BIT
300#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
301#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
302/* The assembler doesn't like typecast */
303#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
304 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
305 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
306#else
307#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
308#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
309#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
310#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200311#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500312
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200313#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500314#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315
316#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
317#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
318
319#define CONFIG_SYS_NAND_BASE 0xffa00000
320#ifdef CONFIG_PHYS_64BIT
321#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
322#else
323#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
324#endif
325#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
326 CONFIG_SYS_NAND_BASE + 0x40000, \
327 CONFIG_SYS_NAND_BASE + 0x80000,\
328 CONFIG_SYS_NAND_BASE + 0xC0000}
329#define CONFIG_SYS_MAX_NAND_DEVICE 4
330#define CONFIG_MTD_NAND_VERIFY_WRITE
331#define CONFIG_CMD_NAND 1
332#define CONFIG_NAND_FSL_ELBC 1
333#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
334
335/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500336#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
338 | BR_PS_8 /* Port Size = 8bit */ \
339 | BR_MS_FCM /* MSEL = FCM */ \
340 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500341#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500342 | OR_FCM_PGS /* Large Page*/ \
343 | OR_FCM_CSCT \
344 | OR_FCM_CST \
345 | OR_FCM_CHT \
346 | OR_FCM_SCY_1 \
347 | OR_FCM_TRLX \
348 | OR_FCM_EHTR)
349
350#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
351#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500352#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
353#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500354
355#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
356 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
357 | BR_PS_8 /* Port Size = 8bit */ \
358 | BR_MS_FCM /* MSEL = FCM */ \
359 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500360#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500361#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
362 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
363 | BR_PS_8 /* Port Size = 8bit */ \
364 | BR_MS_FCM /* MSEL = FCM */ \
365 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500366#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500367
368#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
369 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
370 | BR_PS_8 /* Port Size = 8bit */ \
371 | BR_MS_FCM /* MSEL = FCM */ \
372 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500373#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500374
375/* Serial Port - controlled on board with jumper J8
376 * open - index 2
377 * shorted - index 1
378 */
379#define CONFIG_CONS_INDEX 1
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500380#define CONFIG_SYS_NS16550
381#define CONFIG_SYS_NS16550_SERIAL
382#define CONFIG_SYS_NS16550_REG_SIZE 1
383#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
384
385#define CONFIG_SYS_BAUDRATE_TABLE \
386 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
387
388#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
389#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
390
391/* Use the HUSH parser */
392#define CONFIG_SYS_HUSH_PARSER
393#ifdef CONFIG_SYS_HUSH_PARSER
394#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
395#endif
396
397/*
398 * Pass open firmware flat tree
399 */
400#define CONFIG_OF_LIBFDT 1
401#define CONFIG_OF_BOARD_SETUP 1
402#define CONFIG_OF_STDOUT_VIA_ALIAS 1
403
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500404/* I2C */
405#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
406#define CONFIG_HARD_I2C /* I2C with hardware support */
407#undef CONFIG_SOFT_I2C /* I2C bit-banged */
408#define CONFIG_I2C_MULTI_BUS
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500409#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
410#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
411#define CONFIG_SYS_I2C_SLAVE 0x7F
412#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
413#define CONFIG_SYS_I2C_OFFSET 0x3000
414#define CONFIG_SYS_I2C2_OFFSET 0x3100
415
416/*
417 * I2C2 EEPROM
418 */
419#define CONFIG_ID_EEPROM
420#ifdef CONFIG_ID_EEPROM
421#define CONFIG_SYS_I2C_EEPROM_NXID
422#endif
423#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
424#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
425#define CONFIG_SYS_EEPROM_BUS_NUM 0
426
427/*
Jerry Huang21dd9af2011-01-24 17:09:56 +0000428 * eSPI - Enhanced SPI
429 */
430#define CONFIG_FSL_ESPI
431
432#define CONFIG_SPI_FLASH
433#define CONFIG_SPI_FLASH_SPANSION
434
435#define CONFIG_CMD_SF
436#define CONFIG_SF_DEFAULT_SPEED 10000000
437#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
438
439/*
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500440 * General PCI
441 * Memory space is mapped 1-1, but I/O space must start from 0.
442 */
443
444/* controller 3, Slot 1, tgtid 3, Base address b000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600445#define CONFIG_SYS_PCIE3_NAME "Slot 1"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500446#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
447#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500448#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500449#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
450#else
451#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
452#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
453#endif
454#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
455#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
456#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
457#ifdef CONFIG_PHYS_64BIT
458#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
459#else
460#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
461#endif
462#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
463
464/* controller 2, direct to uli, tgtid 2, Base address 9000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600465#define CONFIG_SYS_PCIE2_NAME "ULI"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500466#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
467#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500468#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500469#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
470#else
471#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
472#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
473#endif
474#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
475#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
476#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
477#ifdef CONFIG_PHYS_64BIT
478#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
479#else
480#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
481#endif
482#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
483
484/* controller 1, Slot 2, tgtid 1, Base address a000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600485#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500486#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
487#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500488#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500489#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
490#else
491#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
492#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
493#endif
494#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
495#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
496#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
497#ifdef CONFIG_PHYS_64BIT
498#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
499#else
500#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
501#endif
502#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
503
504#if defined(CONFIG_PCI)
505
506/*PCIE video card used*/
507#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
508
509/* video */
510#define CONFIG_VIDEO
511
512#if defined(CONFIG_VIDEO)
513#define CONFIG_BIOSEMU
514#define CONFIG_CFB_CONSOLE
515#define CONFIG_VIDEO_SW_CURSOR
516#define CONFIG_VGA_AS_SINGLE_DEVICE
517#define CONFIG_ATI_RADEON_FB
518#define CONFIG_VIDEO_LOGO
519/*#define CONFIG_CONSOLE_CURSOR*/
520#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
521#endif
522
Li Yang28a096e2010-12-30 11:17:44 -0600523/* SRIO1 uses the same window as PCIE2 mem window */
524#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
525#ifdef CONFIG_PHYS_64BIT
526#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
527#else
528#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
529#endif
530#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
531
532/* SRIO2 uses the same window as PCIE1 mem window */
533#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
534#ifdef CONFIG_PHYS_64BIT
535#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
536#else
537#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
538#endif
539#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
540
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500541#define CONFIG_NET_MULTI
542#define CONFIG_PCI_PNP /* do pci plug-and-play */
543
544#undef CONFIG_EEPRO100
545#undef CONFIG_TULIP
546#define CONFIG_RTL8139
547
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500548#ifndef CONFIG_PCI_PNP
549 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
550 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
551 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
552#endif
553
554#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
555#define CONFIG_DOS_PARTITION
556#define CONFIG_SCSI_AHCI
557
558#ifdef CONFIG_SCSI_AHCI
559#define CONFIG_SATA_ULI5288
560#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
561#define CONFIG_SYS_SCSI_MAX_LUN 1
562#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
563#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
564#endif /* SCSI */
565
566#endif /* CONFIG_PCI */
567
568
569#if defined(CONFIG_TSEC_ENET)
570
571#ifndef CONFIG_NET_MULTI
572#define CONFIG_NET_MULTI 1
573#endif
574
575#define CONFIG_MII 1 /* MII PHY management */
576#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
577#define CONFIG_TSEC1 1
578#define CONFIG_TSEC1_NAME "eTSEC1"
579#define CONFIG_TSEC2 1
580#define CONFIG_TSEC2_NAME "eTSEC2"
581#define CONFIG_TSEC3 1
582#define CONFIG_TSEC3_NAME "eTSEC3"
583
584#define CONFIG_PIXIS_SGMII_CMD
585#define CONFIG_FSL_SGMII_RISER 1
586#define SGMII_RISER_PHY_OFFSET 0x1b
587
588#ifdef CONFIG_FSL_SGMII_RISER
589#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
590#endif
591
592#define TSEC1_PHY_ADDR 0
593#define TSEC2_PHY_ADDR 1
594#define TSEC3_PHY_ADDR 2
595
596#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
597#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
598#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
599
600#define TSEC1_PHYIDX 0
601#define TSEC2_PHYIDX 0
602#define TSEC3_PHYIDX 0
603
604#define CONFIG_ETHPRIME "eTSEC1"
605
606#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
607#endif /* CONFIG_TSEC_ENET */
608
609/*
610 * Environment
611 */
Jerry Huang1ac63e42011-01-24 17:09:54 +0000612#if defined(CONFIG_SDCARD)
613#define CONFIG_ENV_IS_IN_MMC
614#define CONFIG_ENV_SIZE 0x2000
615#define CONFIG_SYS_MMC_ENV_DEV 0
Jerry Huang21dd9af2011-01-24 17:09:56 +0000616#elif defined(CONFIG_SPIFLASH)
617#define CONFIG_ENV_IS_IN_SPI_FLASH
618#define CONFIG_ENV_SPI_BUS 0
619#define CONFIG_ENV_SPI_CS 0
620#define CONFIG_ENV_SPI_MAX_HZ 10000000
621#define CONFIG_ENV_SPI_MODE 0
622#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
623#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
624#define CONFIG_ENV_SECT_SIZE 0x10000
Jerry Huang1ac63e42011-01-24 17:09:54 +0000625#else
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500626#define CONFIG_ENV_IS_IN_FLASH 1
627#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
628#define CONFIG_ENV_ADDR 0xfff80000
629#else
630#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
631#endif
632#define CONFIG_ENV_SIZE 0x2000
633#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Jerry Huang1ac63e42011-01-24 17:09:54 +0000634#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500635
636#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
637#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
638
639/*
640 * Command line configuration.
641 */
642#include <config_cmd_default.h>
643
644#define CONFIG_CMD_IRQ
645#define CONFIG_CMD_PING
646#define CONFIG_CMD_I2C
647#define CONFIG_CMD_MII
648#define CONFIG_CMD_ELF
649#define CONFIG_CMD_IRQ
650#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500651#define CONFIG_CMD_REGINFO
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500652
653#if defined(CONFIG_PCI)
654#define CONFIG_CMD_PCI
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500655#define CONFIG_CMD_NET
656#define CONFIG_CMD_SCSI
657#define CONFIG_CMD_EXT2
658#endif
659
Roy Zang0ead6f22009-09-10 14:44:48 +0800660/*
661 * USB
662 */
Jerry Huang9c4d8762011-01-24 17:09:53 +0000663#define CONFIG_USB_EHCI
664
665#ifdef CONFIG_USB_EHCI
Roy Zang0ead6f22009-09-10 14:44:48 +0800666#define CONFIG_CMD_USB
667#define CONFIG_USB_STORAGE
Roy Zang0ead6f22009-09-10 14:44:48 +0800668#define CONFIG_USB_EHCI_FSL
669#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Jerry Huang9c4d8762011-01-24 17:09:53 +0000670#endif
Roy Zang0ead6f22009-09-10 14:44:48 +0800671
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500672#undef CONFIG_WATCHDOG /* watchdog disabled */
673
674/*
Jerry Huang9c4d8762011-01-24 17:09:53 +0000675 * SDHC/MMC
676 */
677#define CONFIG_MMC
678
679#ifdef CONFIG_MMC
680#define CONFIG_FSL_ESDHC
681#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
682#define CONFIG_CMD_MMC
683#define CONFIG_GENERIC_MMC
684#endif
685
686#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
687#define CONFIG_CMD_EXT2
688#define CONFIG_CMD_FAT
689#define CONFIG_DOS_PARTITION
690#endif
691
692/*
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500693 * Miscellaneous configurable options
694 */
695#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500696#define CONFIG_CMDLINE_EDITING /* Command-line editing */
697#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500698#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
699#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
700#if defined(CONFIG_CMD_KGDB)
701#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
702#else
703#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
704#endif
705#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
706#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
707#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
708#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
709
710/*
711 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500712 * have to be in the first 64 MB of memory, since this is
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500713 * the maximum mapped by the Linux kernel during initialization.
714 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500715#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
716#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500717
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500718#if defined(CONFIG_CMD_KGDB)
719#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
720#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
721#endif
722
723/*
724 * Environment Configuration
725 */
726
727/* The mac addresses for all ethernet interface */
728#if defined(CONFIG_TSEC_ENET)
729#define CONFIG_HAS_ETH0
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500730#define CONFIG_HAS_ETH1
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500731#define CONFIG_HAS_ETH2
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500732#endif
733
734#define CONFIG_IPADDR 192.168.1.254
735
736#define CONFIG_HOSTNAME unknown
737#define CONFIG_ROOTPATH /opt/nfsroot
738#define CONFIG_BOOTFILE uImage
739#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
740
741#define CONFIG_SERVERIP 192.168.1.1
742#define CONFIG_GATEWAYIP 192.168.1.1
743#define CONFIG_NETMASK 255.255.255.0
744
745/* default location for tftp and bootm */
746#define CONFIG_LOADADDR 1000000
747
748#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
749#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
750
751#define CONFIG_BAUDRATE 115200
752
753#define CONFIG_EXTRA_ENV_SETTINGS \
Li Yangccc4a8d2011-01-24 17:09:52 +0000754 "perf_mode=performance\0" \
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000755 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
756 "usb1:dr_mode=host,phy_type=ulpi\0" \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500757 "netdev=eth0\0" \
758 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
759 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200760 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
761 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
762 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
763 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
764 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Li Yangccc4a8d2011-01-24 17:09:52 +0000765 "satabootcmd=setenv bootargs root=/dev/$bdev rw " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr - $fdtaddr" \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500770 "consoledev=ttyS0\0" \
771 "ramdiskaddr=2000000\0" \
772 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
773 "fdtaddr=c00000\0" \
Li Yangccc4a8d2011-01-24 17:09:52 +0000774 "othbootargs=cache-sram-size=0x10000\0" \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500775 "fdtfile=p2020ds/p2020ds.dtb\0" \
Li Yangccc4a8d2011-01-24 17:09:52 +0000776 "bdev=sda3\0" \
777 "partition=scsi 0:0\0"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500778
779#define CONFIG_HDBOOT \
780 "setenv bootargs root=/dev/$bdev rw " \
781 "console=$consoledev,$baudrate $othbootargs;" \
Li Yangccc4a8d2011-01-24 17:09:52 +0000782 "ext2load $partition $loadaddr $bootfile;" \
783 "ext2load $partition $fdtaddr $fdtfile;" \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500784 "bootm $loadaddr - $fdtaddr"
785
786#define CONFIG_NFSBOOTCOMMAND \
787 "setenv bootargs root=/dev/nfs rw " \
788 "nfsroot=$serverip:$rootpath " \
789 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
790 "console=$consoledev,$baudrate $othbootargs;" \
791 "tftp $loadaddr $bootfile;" \
792 "tftp $fdtaddr $fdtfile;" \
793 "bootm $loadaddr - $fdtaddr"
794
795#define CONFIG_RAMBOOTCOMMAND \
796 "setenv bootargs root=/dev/ram rw " \
797 "console=$consoledev,$baudrate $othbootargs;" \
798 "tftp $ramdiskaddr $ramdiskfile;" \
799 "tftp $loadaddr $bootfile;" \
800 "tftp $fdtaddr $fdtfile;" \
801 "bootm $loadaddr $ramdiskaddr $fdtaddr"
802
803#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
804
805#endif /* __CONFIG_H */