blob: 4fc5262bc17ea86b33af686c6c60b6b8426e4c41 [file] [log] [blame]
Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1 /* this is a PPC405 CPU */
28#define CONFIG_4xx 1 /* member of PPC4xx family */
29#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
30
31#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
32
33/*
34 * Include common defines/options for all AMCC eval boards
35 */
36#define CONFIG_HOSTNAME dlvsion-10g
37#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
38#include "amcc-common.h"
39
40#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
41#define CONFIG_LAST_STAGE_INIT
42
43#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
44
Dirk Eibach6cfa9ee2011-04-06 13:53:50 +020045#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
46#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
47#define CONFIG_AUTOBOOT_STOP_STR " "
48
Dirk Eibach2da0fc02011-01-21 09:31:21 +010049/*
50 * Configure PLL
51 */
52#define PLLMR0_DEFAULT PLLMR0_266_133_66
53#define PLLMR1_DEFAULT PLLMR1_266_133_66
54
55/* new uImage format support */
56#define CONFIG_FIT
57#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
58
59#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
60
61/*
62 * Default environment variables
63 */
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 CONFIG_AMCC_DEF_ENV \
66 CONFIG_AMCC_DEF_ENV_POWERPC \
67 CONFIG_AMCC_DEF_ENV_NOR_UPD \
68 "kernel_addr=fc000000\0" \
69 "fdt_addr=fc1e0000\0" \
70 "ramdisk_addr=fc200000\0" \
71 ""
72
73#define CONFIG_PHY_ADDR 4 /* PHY address */
74#define CONFIG_HAS_ETH0
75#define CONFIG_HAS_ETH1
76#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
77#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
78
79/*
80 * Commands additional to the ones defined in amcc-common.h
81 */
82#define CONFIG_CMD_CACHE
83#undef CONFIG_CMD_EEPROM
84
85/*
86 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
87 */
88#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
89
90/* SDRAM timings used in datasheet */
91#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
92#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
93#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
94#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
95#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
96
97/*
98 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
99 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
100 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
101 * The Linux BASE_BAUD define should match this configuration.
102 * baseBaud = cpuClock/(uartDivisor*16)
103 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
104 * set Linux BASE_BAUD to 403200.
105 */
106#define CONFIG_CONS_INDEX 1 /* Use UART0 */
107#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
108#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
109#define CONFIG_SYS_BASE_BAUD 691200
110
111/*
112 * I2C stuff
113 */
114#define CONFIG_SYS_I2C_SPEED 100000
115
116/* Temp sensor/hwmon/dtt */
117#define CONFIG_DTT_LM63 1 /* National LM63 */
Dirk Eibach8aa50542011-04-18 10:42:19 +0200118#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100119#define CONFIG_DTT_PWM_LOOKUPTABLE \
Dirk Eibach6c57c882011-04-06 13:53:49 +0200120 { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
121 { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100122#define CONFIG_DTT_TACH_LIMIT 0xa10
123
124/* EBC peripherals */
125
126#define CONFIG_SYS_FLASH_BASE 0xFC000000
127#define CONFIG_SYS_FPGA0_BASE 0x7f100000
128#define CONFIG_SYS_FPGA1_BASE 0x7f200000
129#define CONFIG_SYS_LATCH_BASE 0x7f300000
130
131#define CONFIG_SYS_FPGA_BASE(k) \
132 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
133
134#define CONFIG_SYS_FPGA_DONE(k) \
135 (k ? 0x2000 : 0x1000)
136
137#define CONFIG_SYS_FPGA_COUNT 2
138
139#define CONFIG_SYS_LATCH0_RESET 0xffff
140#define CONFIG_SYS_LATCH0_BOOT 0xffff
141#define CONFIG_SYS_LATCH1_RESET 0xffcf
142#define CONFIG_SYS_LATCH1_BOOT 0xffff
143
Dirk Eibach5cb41002011-04-06 13:53:46 +0200144#define CONFIG_SYS_FPGA_NO_RFL_HI
145
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100146/*
147 * FLASH organization
148 */
149#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
150#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
151
152#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
153
154#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
155#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
156
157#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
159
160#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
161#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
162
163#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
164#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
165
166#ifdef CONFIG_ENV_IS_IN_FLASH
167#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
168#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
169#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
170
171/* Address and size of Redundant Environment Sector */
172#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
173#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
174#endif
175
176/*
177 * PPC405 GPIO Configuration
178 */
179#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
180{ \
181/* GPIO Core 0 */ \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
184{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
185{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
186{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
187{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
188{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
189{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
190{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
191{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
192{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
193{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
194{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
195{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
196{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
197{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
198{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
199{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
200{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
201{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
202{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
206{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
207{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
208{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
210{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
211{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
213{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
214} \
215}
216
217/*
218 * Definitions for initial stack pointer and data area (in data cache)
219 */
220/* use on chip memory (OCM) for temperary stack until sdram is tested */
221#define CONFIG_SYS_TEMP_STACK_OCM 1
222
223/* On Chip Memory location */
224#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
225#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
226#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
227#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
228
229#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
230#define CONFIG_SYS_GBL_DATA_OFFSET \
231 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
232#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233
234/*
235 * External Bus Controller (EBC) Setup
236 */
237
238/* Memory Bank 0 (NOR-flash) */
239#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
240 EBC_BXAP_FWT_ENCODE(8) | \
241 EBC_BXAP_BWT_ENCODE(7) | \
242 EBC_BXAP_BCE_DISABLE | \
243 EBC_BXAP_BCT_2TRANS | \
244 EBC_BXAP_CSN_ENCODE(0) | \
245 EBC_BXAP_OEN_ENCODE(2) | \
246 EBC_BXAP_WBN_ENCODE(2) | \
247 EBC_BXAP_WBF_ENCODE(2) | \
248 EBC_BXAP_TH_ENCODE(4) | \
249 EBC_BXAP_RE_DISABLED | \
250 EBC_BXAP_SOR_NONDELAYED | \
251 EBC_BXAP_BEM_WRITEONLY | \
252 EBC_BXAP_PEN_DISABLED)
253#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
254 EBC_BXCR_BS_64MB | \
255 EBC_BXCR_BU_RW | \
256 EBC_BXCR_BW_16BIT)
257
258/* Memory Bank 1 (FPGA0) */
259#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
260 EBC_BXAP_TWT_ENCODE(5) | \
261 EBC_BXAP_BCE_DISABLE | \
262 EBC_BXAP_BCT_2TRANS | \
263 EBC_BXAP_CSN_ENCODE(0) | \
264 EBC_BXAP_OEN_ENCODE(2) | \
265 EBC_BXAP_WBN_ENCODE(1) | \
266 EBC_BXAP_WBF_ENCODE(1) | \
267 EBC_BXAP_TH_ENCODE(0) | \
268 EBC_BXAP_RE_DISABLED | \
269 EBC_BXAP_SOR_NONDELAYED | \
270 EBC_BXAP_BEM_WRITEONLY | \
271 EBC_BXAP_PEN_DISABLED)
272#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
273 EBC_BXCR_BS_1MB | \
274 EBC_BXCR_BU_RW | \
275 EBC_BXCR_BW_16BIT)
276
277/* Memory Bank 2 (FPGA1) */
278#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
279 EBC_BXAP_TWT_ENCODE(6) | \
280 EBC_BXAP_BCE_DISABLE | \
281 EBC_BXAP_BCT_2TRANS | \
282 EBC_BXAP_CSN_ENCODE(0) | \
283 EBC_BXAP_OEN_ENCODE(2) | \
284 EBC_BXAP_WBN_ENCODE(1) | \
285 EBC_BXAP_WBF_ENCODE(1) | \
286 EBC_BXAP_TH_ENCODE(0) | \
287 EBC_BXAP_RE_DISABLED | \
288 EBC_BXAP_SOR_NONDELAYED | \
289 EBC_BXAP_BEM_WRITEONLY | \
290 EBC_BXAP_PEN_DISABLED)
291#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
292 EBC_BXCR_BS_1MB | \
293 EBC_BXCR_BU_RW | \
294 EBC_BXCR_BW_16BIT)
295
296/* Memory Bank 3 (Latches) */
297#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
298 EBC_BXAP_FWT_ENCODE(8) | \
299 EBC_BXAP_BWT_ENCODE(4) | \
300 EBC_BXAP_BCE_DISABLE | \
301 EBC_BXAP_BCT_2TRANS | \
302 EBC_BXAP_CSN_ENCODE(0) | \
303 EBC_BXAP_OEN_ENCODE(1) | \
304 EBC_BXAP_WBN_ENCODE(1) | \
305 EBC_BXAP_WBF_ENCODE(1) | \
306 EBC_BXAP_TH_ENCODE(2) | \
307 EBC_BXAP_RE_DISABLED | \
308 EBC_BXAP_SOR_NONDELAYED | \
309 EBC_BXAP_BEM_WRITEONLY | \
310 EBC_BXAP_PEN_DISABLED)
311#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
312 EBC_BXCR_BS_1MB | \
313 EBC_BXCR_BU_RW | \
314 EBC_BXCR_BW_16BIT)
315
316/*
317 * OSD Setup
318 */
319#define CONFIG_SYS_ICS8N3QV01
Dirk Eibach7749c842011-04-06 13:53:48 +0200320#define CONFIG_SYS_MPC92469AC
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100321#define CONFIG_SYS_SIL1178
322#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
323
324#endif /* __CONFIG_H */