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dzu@denx.de56a4a632006-04-19 15:27:11 +02001/*
2 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
3 * (C) Copyright 2006 DENX Software Engineering
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26
Jon Loeliger3fe00102007-07-09 18:38:39 -050027#if defined(CONFIG_CMD_NAND)
dzu@denx.de56a4a632006-04-19 15:27:11 +020028
29#include <nand.h>
30
31#if defined(CONFIG_IDS852_REV1)
32/*
33 * hardware specific access to control-lines
34 */
35static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
36{
37 struct nand_chip *this = mtd->priv;
38
39 switch(cmd) {
Wolfgang Denk610cf362006-05-03 01:24:04 +020040 case NAND_CTL_SETCLE:
41 this->IO_ADDR_W += 2;
42 break;
43 case NAND_CTL_CLRCLE:
44 this->IO_ADDR_W -= 2;
45 break;
46 case NAND_CTL_SETALE:
47 this->IO_ADDR_W += 1;
48 break;
49 case NAND_CTL_CLRALE:
50 this->IO_ADDR_W -= 1;
51 break;
52 case NAND_CTL_SETNCE:
53 case NAND_CTL_CLRNCE:
54 /* nop */
55 break;
dzu@denx.de56a4a632006-04-19 15:27:11 +020056 }
57}
58#elif defined(CONFIG_IDS852_REV2)
59/*
60 * hardware specific access to control-lines
61 */
62static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
63{
64 struct nand_chip *this = mtd->priv;
65
66 switch(cmd) {
Wolfgang Denk610cf362006-05-03 01:24:04 +020067 case NAND_CTL_SETCLE:
68 *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
69 break;
70 case NAND_CTL_CLRCLE:
71 *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
72 break;
73 case NAND_CTL_SETALE:
74 *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
75 break;
76 case NAND_CTL_CLRALE:
77 *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
78 break;
79 case NAND_CTL_SETNCE:
80 *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
81 break;
82 case NAND_CTL_CLRNCE:
83 *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
84 break;
dzu@denx.de56a4a632006-04-19 15:27:11 +020085 }
86}
87#else
88#error Unknown IDS852 module revision
89#endif
90
91/*
92 * Board-specific NAND initialization. The following members of the
93 * argument are board-specific (per include/linux/mtd/nand.h):
94 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
95 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
96 * - hwcontrol: hardwarespecific function for accesing control-lines
97 * - dev_ready: hardwarespecific function for accesing device ready/busy line
98 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
99 * only be provided if a hardware ECC is available
100 * - eccmode: mode of ecc, see defines
101 * - chip_delay: chip dependent delay for transfering data from array to
102 * read regs (tR)
103 * - options: various chip options. They can partly be set to inform
104 * nand_scan about special functionality. See the defines for further
105 * explanation
106 * Members with a "?" were not set in the merged testing-NAND branch,
107 * so they are not set here either.
108 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100109int board_nand_init(struct nand_chip *nand)
dzu@denx.de56a4a632006-04-19 15:27:11 +0200110{
111
112 nand->hwcontrol = nc650_hwcontrol;
113 nand->eccmode = NAND_ECC_SOFT;
114 nand->chip_delay = 12;
115/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
Heiko Schocherfa230442006-12-21 17:17:02 +0100116 return 0;
dzu@denx.de56a4a632006-04-19 15:27:11 +0200117}
Jon Loeliger3fe00102007-07-09 18:38:39 -0500118#endif