blob: b69741ae6833f9b40fabf06e26d56b54ee272497 [file] [log] [blame]
wdenk5da627a2003-10-09 20:09:04 +00001/* Only eth0 supported for now
2 *
3 * (C) Copyright 2003
4 * Thomas.Lange@corelatus.se
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk265817c2005-09-25 00:53:22 +020016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk5da627a2003-10-09 20:09:04 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#include <config.h>
25
26#ifdef CONFIG_AU1X00
27
Wolfgang Denk265817c2005-09-25 00:53:22 +020028#if defined(CFG_DISCOVER_PHY)
29#error "PHY not supported yet"
wdenk5da627a2003-10-09 20:09:04 +000030/* We just assume that we are running 100FD for now */
31/* We all use switches, right? ;-) */
32#endif
33
wdenka2663ea2003-12-07 18:32:37 +000034/* I assume ethernet behaves like au1000 */
35
wdenk5da627a2003-10-09 20:09:04 +000036#ifdef CONFIG_AU1000
37/* Base address differ between cpu:s */
38#define ETH0_BASE AU1000_ETH0_BASE
39#define MAC0_ENABLE AU1000_MAC0_ENABLE
40#else
wdenka2663ea2003-12-07 18:32:37 +000041#ifdef CONFIG_AU1100
42#define ETH0_BASE AU1100_ETH0_BASE
43#define MAC0_ENABLE AU1100_MAC0_ENABLE
44#else
45#ifdef CONFIG_AU1500
46#define ETH0_BASE AU1500_ETH0_BASE
47#define MAC0_ENABLE AU1500_MAC0_ENABLE
48#else
wdenkff36fd82005-01-09 22:28:56 +000049#ifdef CONFIG_AU1550
50#define ETH0_BASE AU1550_ETH0_BASE
51#define MAC0_ENABLE AU1550_MAC0_ENABLE
52#else
wdenka2663ea2003-12-07 18:32:37 +000053#error "No valid cpu set"
54#endif
55#endif
wdenk5da627a2003-10-09 20:09:04 +000056#endif
wdenkff36fd82005-01-09 22:28:56 +000057#endif
wdenk5da627a2003-10-09 20:09:04 +000058
59#include <common.h>
60#include <malloc.h>
61#include <net.h>
62#include <command.h>
63#include <asm/io.h>
64#include <asm/au1x00.h>
65
Jon Loeliger44312832007-07-09 19:06:00 -050066#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020067#include <miiphy.h>
68#endif
69
wdenk5da627a2003-10-09 20:09:04 +000070/* Ethernet Transmit and Receive Buffers */
71#define DBUF_LENGTH 1520
72#define PKT_MAXBUF_SIZE 1518
73
74static char txbuf[DBUF_LENGTH];
75
76static int next_tx;
77static int next_rx;
78
79/* 4 rx and 4 tx fifos */
80#define NO_OF_FIFOS 4
81
82typedef struct{
83 u32 status;
84 u32 addr;
85 u32 len; /* Only used for tx */
86 u32 not_used;
87} mac_fifo_t;
88
89mac_fifo_t mac_fifo[NO_OF_FIFOS];
90
91#define MAX_WAIT 1000
92
93static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
94 volatile mac_fifo_t *fifo_tx =
95 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
96 int i;
97 int res;
98
99 /* tx fifo should always be idle */
100 fifo_tx[next_tx].len = length;
101 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
102 au_sync();
103
104 udelay(1);
105 i=0;
106 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
107 if(i>MAX_WAIT){
108 printf("TX timeout\n");
109 break;
110 }
111 udelay(1);
112 i++;
113 }
114
115 /* Clear done bit */
116 fifo_tx[next_tx].addr = 0;
117 fifo_tx[next_tx].len = 0;
118 au_sync();
119
120 res = fifo_tx[next_tx].status;
121
122 next_tx++;
123 if(next_tx>=NO_OF_FIFOS){
124 next_tx=0;
125 }
126 return(res);
127}
128
129static int au1x00_recv(struct eth_device* dev){
130 volatile mac_fifo_t *fifo_rx =
131 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
132
133 int length;
134 u32 status;
135
136 for(;;){
137 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
138 /* Nothing has been received */
139 return(-1);
140 }
141
142 status = fifo_rx[next_rx].status;
143
144 length = status&0x3FFF;
145
146 if(status&RX_ERROR){
147 printf("Rx error 0x%x\n", status);
148 }
149 else{
150 /* Pass the packet up to the protocol layers. */
151 NetReceive(NetRxPackets[next_rx], length - 4);
152 }
153
154 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
155
156 next_rx++;
157 if(next_rx>=NO_OF_FIFOS){
158 next_rx=0;
159 }
160 } /* for */
161
162 return(0); /* Does anyone use this? */
163}
164
165static int au1x00_init(struct eth_device* dev, bd_t * bd){
166
167 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
168 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
169 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
170 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
171 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
172 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
173 volatile mac_fifo_t *fifo_tx =
174 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
175 volatile mac_fifo_t *fifo_rx =
176 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
177 int i;
178
Wolfgang Denk4bc12f12005-09-24 22:05:40 +0200179 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
180 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
wdenk5da627a2003-10-09 20:09:04 +0000181
182 /* We have to enable clocks before releasing reset */
183 *macen = MAC_EN_CLOCK_ENABLE;
184 udelay(10);
185
186 /* Enable MAC0 */
187 /* We have to release reset before accessing registers */
188 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
189 MAC_EN_RESET1|MAC_EN_RESET2;
190 udelay(10);
191
192 for(i=0;i<NO_OF_FIFOS;i++){
193 fifo_tx[i].len = 0;
194 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
195 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
196 }
197
198 /* Put mac addr in little endian */
wdenk5da627a2003-10-09 20:09:04 +0000199#define ea eth_get_dev()->enetaddr
Wolfgang Denk265817c2005-09-25 00:53:22 +0200200 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
201 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
202 (ea[1] << 8) | (ea[0] ) ;
wdenk5da627a2003-10-09 20:09:04 +0000203#undef ea
wdenk5da627a2003-10-09 20:09:04 +0000204 *mac_mcast_low = 0;
205 *mac_mcast_high = 0;
206
wdenk63f34912004-01-02 15:01:32 +0000207 /* Make sure the MAC buffer is in the correct endian mode */
208#ifdef __LITTLE_ENDIAN
209 *mac_ctrl = MAC_FULL_DUPLEX;
210 udelay(1);
211 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
212#else
wdenk5da627a2003-10-09 20:09:04 +0000213 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
214 udelay(1);
215 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
wdenk63f34912004-01-02 15:01:32 +0000216#endif
wdenk5da627a2003-10-09 20:09:04 +0000217
218 return(1);
219}
220
221static void au1x00_halt(struct eth_device* dev){
222}
223
224int au1x00_enet_initialize(bd_t *bis){
225 struct eth_device* dev;
226
Wolfgang Denk95515302006-03-13 01:00:22 +0100227 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
228 puts ("malloc failed\n");
229 return 0;
230 }
231
wdenk5da627a2003-10-09 20:09:04 +0000232 memset(dev, 0, sizeof *dev);
233
Wolfgang Denk95515302006-03-13 01:00:22 +0100234 sprintf(dev->name, "Au1X00 ethernet");
wdenk5da627a2003-10-09 20:09:04 +0000235 dev->iobase = 0;
236 dev->priv = 0;
237 dev->init = au1x00_init;
238 dev->halt = au1x00_halt;
239 dev->send = au1x00_send;
240 dev->recv = au1x00_recv;
241
242 eth_register(dev);
243
Jon Loeliger44312832007-07-09 19:06:00 -0500244#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200245 miiphy_register(dev->name,
246 au1x00_miiphy_read, au1x00_miiphy_write);
247#endif
248
wdenk5da627a2003-10-09 20:09:04 +0000249 return 1;
250}
251
Jon Loeliger44312832007-07-09 19:06:00 -0500252#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200253int au1x00_miiphy_read(char *devname, unsigned char addr,
254 unsigned char reg, unsigned short * value)
Wolfgang Denk265817c2005-09-25 00:53:22 +0200255{
256 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
257 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
258 u32 mii_control;
259 unsigned int timedout = 20;
260
261 while (*mii_control_reg & MAC_MII_BUSY) {
262 udelay(1000);
263 if (--timedout == 0) {
264 printf("au1x00_eth: miiphy_read busy timeout!!\n");
265 return -1;
266 }
267 }
268
269 mii_control = MAC_SET_MII_SELECT_REG(reg) |
270 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
271
272 *mii_control_reg = mii_control;
273
274 timedout = 20;
275 while (*mii_control_reg & MAC_MII_BUSY) {
276 udelay(1000);
277 if (--timedout == 0) {
278 printf("au1x00_eth: miiphy_read busy timeout!!\n");
279 return -1;
280 }
281 }
282 *value = *mii_data_reg;
283 return 0;
284}
285
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200286int au1x00_miiphy_write(char *devname, unsigned char addr,
287 unsigned char reg, unsigned short value)
Wolfgang Denk265817c2005-09-25 00:53:22 +0200288{
289 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
290 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
291 u32 mii_control;
292 unsigned int timedout = 20;
293
294 while (*mii_control_reg & MAC_MII_BUSY) {
295 udelay(1000);
296 if (--timedout == 0) {
297 printf("au1x00_eth: miiphy_write busy timeout!!\n");
298 return;
299 }
300 }
301
302 mii_control = MAC_SET_MII_SELECT_REG(reg) |
303 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
304
305 *mii_data_reg = value;
306 *mii_control_reg = mii_control;
307 return 0;
308}
Jon Loeliger44312832007-07-09 19:06:00 -0500309#endif
Wolfgang Denk265817c2005-09-25 00:53:22 +0200310
wdenk5da627a2003-10-09 20:09:04 +0000311#endif /* CONFIG_AU1X00 */