blob: 8e51d2d3c05bebb5354fe5465dd9f4e4c75500e1 [file] [log] [blame]
Stefan Roesea4c8d132006-06-02 16:18:04 +02001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * pcs440ep.h - configuration for PCS440EP board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
34#define CONFIG_440EP 1 /* Specific PPC440EP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020035#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roesea4c8d132006-06-02 16:18:04 +020036#define CONFIG_4xx 1 /* ... PPC4xx family */
37#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
38
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
41
42/*-----------------------------------------------------------------------
43 * Base addresses -- Note these are effective addresses where the
44 * actual resources get mapped (not physical addresses)
45 *----------------------------------------------------------------------*/
Wolfgang Denke461a242006-06-07 11:36:02 +020046#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
Stefan Roesea4c8d132006-06-02 16:18:04 +020047#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
48#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
49#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
50#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
51#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
52#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
53#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
54#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
55
56/*Don't change either of these*/
57#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
58#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
59/*Don't change either of these*/
60
61#define CFG_USB_DEVICE 0x50000000
62#define CFG_BOOT_BASE_ADDR 0xf0000000
63
64/*-----------------------------------------------------------------------
65 * Initial RAM & stack pointer (placed in SDRAM)
66 *----------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +020067#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
Stefan Roesea4c8d132006-06-02 16:18:04 +020068#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
69#define CFG_INIT_RAM_END (8 << 10)
70#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
71#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
72#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
73
74/*-----------------------------------------------------------------------
75 * Serial Port
76 *----------------------------------------------------------------------*/
77#undef CFG_EXT_SERIAL_CLOCK /* no external clk used */
78#define CONFIG_BAUDRATE 115200
79#define CONFIG_SERIAL_MULTI 1
80/*define this if you want console on UART1*/
81#undef CONFIG_UART1_CONSOLE
82
83#define CFG_BAUDRATE_TABLE \
84 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
85
86/*-----------------------------------------------------------------------
87 * Environment
88 *----------------------------------------------------------------------*/
89#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
90
91/*-----------------------------------------------------------------------
92 * FLASH related
93 *----------------------------------------------------------------------*/
94#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
95#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
96
97#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
98#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
99
100#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
101#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
102#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
103
104#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
105
106#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200107#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200108#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
Heiko Schocher566a4942007-06-22 19:11:54 +0200109#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
110
111#define CONFIG_ENV_OVERWRITE 1
Stefan Roesea4c8d132006-06-02 16:18:04 +0200112
113/* Address and size of Redundant Environment Sector */
114#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
115#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
116#endif /* CFG_ENV_IS_IN_FLASH */
117
Heiko Schocher566a4942007-06-22 19:11:54 +0200118#define ENV_NAME_REVLEV "revision_level"
119#define ENV_NAME_SOLDER "solder_switch"
120#define ENV_NAME_DIP "dip"
121
Stefan Roesea4c8d132006-06-02 16:18:04 +0200122/*-----------------------------------------------------------------------
123 * DDR SDRAM
124 *----------------------------------------------------------------------*/
125#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
126#undef CONFIG_DDR_ECC /* don't use ECC */
Stefan Roeseed4633c2006-06-13 18:55:07 +0200127#define SPD_EEPROM_ADDRESS {0x50}
Heiko Schocher566a4942007-06-22 19:11:54 +0200128#define CONFIG_PROG_SDRAM_TLB 1
Stefan Roesea4c8d132006-06-02 16:18:04 +0200129
130/*-----------------------------------------------------------------------
131 * I2C
132 *----------------------------------------------------------------------*/
133#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
134#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roeseed4633c2006-06-13 18:55:07 +0200135#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200136#define CFG_I2C_SLAVE 0x7F
137
Stefan Roeseed4633c2006-06-13 18:55:07 +0200138#define CFG_I2C_EEPROM_ADDR (0xa4>>1)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200139#define CFG_I2C_EEPROM_ADDR_LEN 1
140#define CFG_EEPROM_PAGE_WRITE_ENABLE
141#define CFG_EEPROM_PAGE_WRITE_BITS 3
142#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
143
144#define CONFIG_PREBOOT "echo;" \
145 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
146 "echo"
147
148#undef CONFIG_BOOTARGS
149
150#define CONFIG_EXTRA_ENV_SETTINGS \
151 "netdev=eth0\0" \
152 "hostname=pcs440ep\0" \
Heiko Schocher566a4942007-06-22 19:11:54 +0200153 "use_eeprom_ethaddr=default\0" \
154 "cs_test=off\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
156 "nfsroot=${serverip}:${rootpath}\0" \
157 "ramargs=setenv bootargs root=/dev/ram rw\0" \
158 "addip=setenv bootargs ${bootargs} " \
159 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
160 ":${hostname}:${netdev}:off panic=1\0" \
161 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
162 "flash_nfs=run nfsargs addip addtty;" \
163 "bootm ${kernel_addr}\0" \
164 "flash_self=run ramargs addip addtty;" \
165 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
166 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
167 "bootm\0" \
168 "rootpath=/opt/eldk/ppc_4xx\0" \
169 "bootfile=/tftpboot/pcs440ep/uImage\0" \
Wolfgang Denke461a242006-06-07 11:36:02 +0200170 "kernel_addr=FFF00000\0" \
171 "ramdisk_addr=FFF00000\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200172 "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
Wolfgang Denke461a242006-06-07 11:36:02 +0200173 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
174 "cp.b 100000 FFFA0000 60000\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200175 "upd=run load;run update\0" \
176 ""
177#define CONFIG_BOOTCOMMAND "run flash_self"
178
179#if 0
180#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
181#else
182#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
183#endif
184
Heiko Schocher566a4942007-06-22 19:11:54 +0200185#define CONFIG_PREBOOT "echo;" \
186 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
187 "echo"
188
189/* check U-Boot image with SHA1 sum */
190#define CONFIG_SHA1_CHECK_UB_IMG 1
191#define CONFIG_SHA1_START CFG_MONITOR_BASE
192#define CONFIG_SHA1_LEN CFG_MONITOR_LEN
193
194/*-----------------------------------------------------------------------
195 * Definitions for status LED
196 */
197#define CONFIG_STATUS_LED 1 /* Status LED enabled */
198#define CONFIG_BOARD_SPECIFIC_LED 1
199
Heiko Schocher96e1d752007-07-11 18:39:11 +0200200#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
Heiko Schocher566a4942007-06-22 19:11:54 +0200201#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
202#define STATUS_LED_STATE STATUS_LED_OFF
Heiko Schocher96e1d752007-07-11 18:39:11 +0200203#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
Heiko Schocher566a4942007-06-22 19:11:54 +0200204#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
205#define STATUS_LED_STATE1 STATUS_LED_ON
Heiko Schocher96e1d752007-07-11 18:39:11 +0200206#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
Heiko Schocher566a4942007-06-22 19:11:54 +0200207#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
208#define STATUS_LED_STATE2 STATUS_LED_OFF
Heiko Schocher96e1d752007-07-11 18:39:11 +0200209#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
Heiko Schocher566a4942007-06-22 19:11:54 +0200210#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
211#define STATUS_LED_STATE3 STATUS_LED_OFF
212
213#define CONFIG_SHOW_BOOT_PROGRESS 1
214
Stefan Roesea4c8d132006-06-02 16:18:04 +0200215#define CONFIG_BAUDRATE 115200
216
217#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
218#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
219
220#define CONFIG_MII 1 /* MII PHY management */
221#define CONFIG_NET_MULTI 1 /* required for netconsole */
222#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
223#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
224#define CONFIG_PHY1_ADDR 2
225
226#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
227
228#define CONFIG_NETCONSOLE /* include NetConsole support */
229
230/* Partitions */
231#define CONFIG_MAC_PARTITION
232#define CONFIG_DOS_PARTITION
233#define CONFIG_ISO_PARTITION
234
235#ifdef CONFIG_440EP
236/* USB */
237#define CONFIG_USB_OHCI
238#define CONFIG_USB_STORAGE
239
240/*Comment this out to enable USB 1.1 device*/
241#define USB_2_0_DEVICE
242#endif /*CONFIG_440EP*/
243
244#ifdef DEBUG
245#define CONFIG_PANIC_HANG
246#else
247#define CONFIG_HW_WATCHDOG /* watchdog */
248#endif
249
Jon Loeliger26a34562007-07-04 22:33:17 -0500250
251/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500252 * BOOTP options
253 */
254#define CONFIG_BOOTP_BOOTFILESIZE
255#define CONFIG_BOOTP_BOOTPATH
256#define CONFIG_BOOTP_GATEWAY
257#define CONFIG_BOOTP_HOSTNAME
258
259
260/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500261 * Command line configuration.
262 */
263#include <config_cmd_default.h>
264#define CONFIG_CMD_ASKENV
265#define CONFIG_CMD_DHCP
266#define CONFIG_CMD_DIAG
267#define CONFIG_CMD_EEPROM
268#define CONFIG_CMD_ELF
269#define CONFIG_CMD_I2C
270#define CONFIG_CMD_IRQ
271#define CONFIG_CMD_MII
272#define CONFIG_CMD_NET
273#define CONFIG_CMD_NFS
274#define CONFIG_CMD_PCI
275#define CONFIG_CMD_PING
276#define CONFIG_CMD_REGINFO
277#define CONFIG_CMD_SDRAM
278#define CONFIG_CMD_EXT2
279#define CONFIG_CMD_FAT
280#define CONFIG_CMD_USB
Stefan Roesea4c8d132006-06-02 16:18:04 +0200281
282
283#define CONFIG_SUPPORT_VFAT
284
Stefan Roesea4c8d132006-06-02 16:18:04 +0200285/*
286 * Miscellaneous configurable options
287 */
288#define CFG_LONGHELP /* undef to save memory */
289#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger26a34562007-07-04 22:33:17 -0500290#if defined(CONFIG_CMD_KGDB)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200291#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
292#else
293#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
294#endif
295#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
296#define CFG_MAXARGS 16 /* max number of command args */
297#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
298
299#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
300#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
301
302#define CFG_LOAD_ADDR 0x100000 /* default load address */
303#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
304#define CONFIG_LYNXKDI 1 /* support kdi files */
305
306#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
307
308/*-----------------------------------------------------------------------
309 * PCI stuff
310 *-----------------------------------------------------------------------
311 */
312/* General PCI */
313#define CONFIG_PCI /* include pci support */
314#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
315#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
316#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
317
318/* Board-specific PCI */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200319#define CFG_PCI_TARGET_INIT
320#define CFG_PCI_MASTER_INIT
321
322#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
323#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
324
325/*
326 * For booting Linux, the board info and command line data
327 * have to be in the first 8 MB of memory, since this is
328 * the maximum mapped by the Linux kernel during initialization.
329 */
330#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
331
332/*-----------------------------------------------------------------------
333 * External Bus Controller (EBC) Setup
334 *----------------------------------------------------------------------*/
335#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
336#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
337
338#define CFG_FLASH FLASH_BASE0_PRELIM
339#define CFG_SRAM 0xF1000000
340#define CFG_FPGA 0xF2000000
341#define CFG_CF1 0xF0000000
342#define CFG_CF2 0xF0100000
343
344/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
345#define CFG_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
346#define CFG_EBC_PB0CR (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
347
348/* Memory Bank 1 (SRAM) initialization */
349#define CFG_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
350#define CFG_EBC_PB1CR (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
351
352/* Memory Bank 2 (FPGA) initialization */
353#define CFG_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
354#define CFG_EBC_PB2CR (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
355
356/* Memory Bank 3 (CompactFlash) initialization */
357#define CFG_EBC_PB3AP 0x080BD400
358#define CFG_EBC_PB3CR (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
359
360/* Memory Bank 4 (CompactFlash) initialization */
361#define CFG_EBC_PB4AP 0x080BD400
362#define CFG_EBC_PB4CR (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
363
364/*-----------------------------------------------------------------------
365 * PPC440 GPIO Configuration
366 */
Stefan Roese85f73732007-06-15 07:39:43 +0200367#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200368{ \
369/* GPIO Core 0 */ \
Stefan Roese85f73732007-06-15 07:39:43 +0200370{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
371{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
372{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
373{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
374{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
375{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
376{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
377{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
378{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
379{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
380{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
381{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
382{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
383{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
384{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
385{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
386{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
387{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
388{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
389{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
390{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
391{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
392{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
393{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
394{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
395{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
396{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
397{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
398{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
399{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
400{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
401{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200402}, \
403{ \
404/* GPIO Core 1 */ \
Stefan Roese85f73732007-06-15 07:39:43 +0200405{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
406{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
407{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
408{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
409{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
410{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
411{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
412{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
413{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
414{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
415{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
416{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
417{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
418{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
419{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
420{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
421{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
422{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
423{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
424{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
425{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
426{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
427{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
428{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
429{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
430{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
431{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
432{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
433{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
434{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
435{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
436{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200437} \
438}
439
440/*-----------------------------------------------------------------------
441 * Cache Configuration
442 */
443#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
444#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeliger26a34562007-07-04 22:33:17 -0500445#if defined(CONFIG_CMD_KGDB)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200446#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
447#endif
448
449/*
450 * Internal Definitions
451 *
452 * Boot Flags
453 */
454#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
455#define BOOTFLAG_WARM 0x02 /* Software reboot */
456
Jon Loeliger26a34562007-07-04 22:33:17 -0500457#if defined(CONFIG_CMD_KGDB)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200458#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
459#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
460#endif
461
Heiko Schocher566a4942007-06-22 19:11:54 +0200462/*-----------------------------------------------------------------------
463 * IDE/ATA stuff Supports IDE harddisk
464 *-----------------------------------------------------------------------
465 */
466
467#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
468
469#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
470#undef CONFIG_IDE_LED /* LED for ide not supported */
471
472#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
473#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
474
475#define CONFIG_IDE_PREINIT 1
476#define CONFIG_IDE_RESET 1
477
478#define CFG_ATA_IDE0_OFFSET 0x0000
479
480#define CFG_ATA_BASE_ADDR CFG_CF1
481
482/* Offset for data I/O */
483#define CFG_ATA_DATA_OFFSET 0
484
485/* Offset for normal register accesses */
486#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
487
488/* Offset for alternate registers */
489#define CFG_ATA_ALT_OFFSET (0x0000)
490
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200491/* These addresses need to be shifted one place to the left
Heiko Schocher566a4942007-06-22 19:11:54 +0200492 * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200493 * These values are shifted
Heiko Schocher566a4942007-06-22 19:11:54 +0200494 */
495#define CFG_ATA_PORT_ADDR(port) ((port) << 1)
496
Stefan Roesea4c8d132006-06-02 16:18:04 +0200497#endif /* __CONFIG_H */