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wdenkf12e5682003-07-07 20:07:54 +00001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
38
39#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
40
41#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
45#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
46
47#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
48
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
52 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
53 "echo"
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=$(serverip):$(rootpath)\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs $(bootargs) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
64 ":$(hostname):$(netdev):off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \
66 "bootm $(kernel_addr)\0" \
67 "flash_self=run ramargs addip;" \
68 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
69 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/NSCU/uImage\0" \
72 "kernel_addr=40080000\0" \
73 "ramdisk_addr=40180000\0" \
74 ""
75#define CONFIG_BOOTCOMMAND "run flash_self"
76
77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85
86#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
87
88#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
90
91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92
93#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
94 CFG_CMD_ASKENV | \
95 CFG_CMD_DHCP | \
96 CFG_CMD_IDE | \
97 CFG_CMD_DATE )
98
99/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
100#include <cmd_confdefs.h>
101
102/*
103 * Miscellaneous configurable options
104 */
105#define CFG_LONGHELP /* undef to save memory */
106#define CFG_PROMPT "=> " /* Monitor Command Prompt */
107
108#if 0
109#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
110#endif
111#ifdef CFG_HUSH_PARSER
112#define CFG_PROMPT_HUSH_PS2 "> "
113#endif
114
115#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
116#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
117#else
118#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
119#endif
120#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
121#define CFG_MAXARGS 16 /* max number of command args */
122#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
123
124#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
125#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
126
127#define CFG_LOAD_ADDR 0x100000 /* default load address */
128
129#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
130
131#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132
133/*
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
137 */
138/*-----------------------------------------------------------------------
139 * Internal Memory Mapped Register
140 */
141#define CFG_IMMR 0xFFF00000
142
143/*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
145 */
146#define CFG_INIT_RAM_ADDR CFG_IMMR
147#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
148#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
149#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
150#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
151
152/*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CFG_SDRAM_BASE _must_ start at 0
156 */
157#define CFG_SDRAM_BASE 0x00000000
158#define CFG_FLASH_BASE 0x40000000
159#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160#define CFG_MONITOR_BASE CFG_FLASH_BASE
161#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
162
163/*
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization.
167 */
168#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
169
170/*-----------------------------------------------------------------------
171 * FLASH organization
172 */
173#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
174#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
175
176#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
177#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
178
179#define CFG_ENV_IS_IN_FLASH 1
180#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
181#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
182#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
183
184/* Address and size of Redundant Environment Sector */
185#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
186#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
187
188/*-----------------------------------------------------------------------
189 * Hardware Information Block
190 */
191#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
192#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
193#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
194
195/*-----------------------------------------------------------------------
196 * Cache Configuration
197 */
198#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
199#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
200#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
201#endif
202
203/*-----------------------------------------------------------------------
204 * SYPCR - System Protection Control 11-9
205 * SYPCR can only be written once after reset!
206 *-----------------------------------------------------------------------
207 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
208 */
209#if defined(CONFIG_WATCHDOG)
210#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
211 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
212#else
213#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
214#endif
215
216/*-----------------------------------------------------------------------
217 * SIUMCR - SIU Module Configuration 11-6
218 *-----------------------------------------------------------------------
219 * PCMCIA config., multi-function pin tri-state
220 */
221#ifndef CONFIG_CAN_DRIVER
222#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
223#else /* we must activate GPL5 in the SIUMCR for CAN */
224#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
225#endif /* CONFIG_CAN_DRIVER */
226
227/*-----------------------------------------------------------------------
228 * TBSCR - Time Base Status and Control 11-26
229 *-----------------------------------------------------------------------
230 * Clear Reference Interrupt Status, Timebase freezing enabled
231 */
232#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
233
234/*-----------------------------------------------------------------------
235 * RTCSC - Real-Time Clock Status and Control Register 11-27
236 *-----------------------------------------------------------------------
237 */
238#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
239
240/*-----------------------------------------------------------------------
241 * PISCR - Periodic Interrupt Status and Control 11-31
242 *-----------------------------------------------------------------------
243 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
244 */
245#define CFG_PISCR (PISCR_PS | PISCR_PITF)
246
247/*-----------------------------------------------------------------------
248 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
249 *-----------------------------------------------------------------------
250 * Reset PLL lock status sticky bit, timer expired status bit and timer
251 * interrupt status bit
252 *
253 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
254 */
255#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
256#define CFG_PLPRCR \
257 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
258#else /* up to 66 MHz we use a 1:1 clock */
259#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
260#endif /* CONFIG_80MHz */
261
262/*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
267 */
268#define SCCR_MASK SCCR_EBDF11
269#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
270#define CFG_SCCR (/* SCCR_TBS | */ \
271 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
272 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
273 SCCR_DFALCD00)
274#else /* up to 66 MHz we use a 1:1 clock */
275#define CFG_SCCR (SCCR_TBS | \
276 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
277 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
278 SCCR_DFALCD00)
279#endif /* CONFIG_80MHz */
280
281/*-----------------------------------------------------------------------
282 * PCMCIA stuff
283 *-----------------------------------------------------------------------
284 *
285 */
286#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
287#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
288#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
289#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
291#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
292#define CFG_PCMCIA_IO_ADDR (0xEC000000)
293#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
294
295/*-----------------------------------------------------------------------
296 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
297 *-----------------------------------------------------------------------
298 */
299
300#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
301
302#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
303#undef CONFIG_IDE_LED /* LED for ide not supported */
304#undef CONFIG_IDE_RESET /* reset for ide not supported */
305
306#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
307#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
308
309#define CFG_ATA_IDE0_OFFSET 0x0000
310
311#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
312
313/* Offset for data I/O */
314#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
315
316/* Offset for normal register accesses */
317#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
318
319/* Offset for alternate registers */
320#define CFG_ATA_ALT_OFFSET 0x0100
321
322/*-----------------------------------------------------------------------
323 *
324 *-----------------------------------------------------------------------
325 *
326 */
327#define CFG_DER 0
328
329/*
330 * Init Memory Controller:
331 *
332 * BR0/1 and OR0/1 (FLASH)
333 */
334
335#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
336#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
337
338/* used to re-map FLASH both when starting from SRAM or FLASH:
339 * restrict access enough to keep SRAM working (if any)
340 * but not too much to meddle with FLASH accesses
341 */
342#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
343#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
344
345/*
346 * FLASH timing:
347 */
348#if defined(CONFIG_80MHz)
349/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
350#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
351 OR_SCY_3_CLK | OR_EHTR | OR_BI)
352#elif defined(CONFIG_66MHz)
353/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
354#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
355 OR_SCY_3_CLK | OR_EHTR | OR_BI)
356#else /* 50 MHz */
357/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
358#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
359 OR_SCY_2_CLK | OR_EHTR | OR_BI)
360#endif /*CONFIG_??MHz */
361
362#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
363#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
364#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
365
366#define CFG_OR1_REMAP CFG_OR0_REMAP
367#define CFG_OR1_PRELIM CFG_OR0_PRELIM
368#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
369
370/*
371 * BR2/3 and OR2/3 (SDRAM)
372 *
373 */
374#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
375#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
376#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
377
378/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
379#define CFG_OR_TIMING_SDRAM 0x00000A00
380
381#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
382#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
383
384#ifndef CONFIG_CAN_DRIVER
385#define CFG_OR3_PRELIM CFG_OR2_PRELIM
386#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
387#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
388#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
389#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
390#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
391#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
392 BR_PS_8 | BR_MS_UPMB | BR_V )
393#endif /* CONFIG_CAN_DRIVER */
394
395/*
396 * Memory Periodic Timer Prescaler
397 *
398 * The Divider for PTA (refresh timer) configuration is based on an
399 * example SDRAM configuration (64 MBit, one bank). The adjustment to
400 * the number of chip selects (NCS) and the actually needed refresh
401 * rate is done by setting MPTPR.
402 *
403 * PTA is calculated from
404 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
405 *
406 * gclk CPU clock (not bus clock!)
407 * Trefresh Refresh cycle * 4 (four word bursts used)
408 *
409 * 4096 Rows from SDRAM example configuration
410 * 1000 factor s -> ms
411 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
412 * 4 Number of refresh cycles per period
413 * 64 Refresh cycle in ms per number of rows
414 * --------------------------------------------
415 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
416 *
417 * 50 MHz => 50.000.000 / Divider = 98
418 * 66 Mhz => 66.000.000 / Divider = 129
419 * 80 Mhz => 80.000.000 / Divider = 156
420 */
421#if defined(CONFIG_80MHz)
422#define CFG_MAMR_PTA 156
423#elif defined(CONFIG_66MHz)
424#define CFG_MAMR_PTA 129
425#else /* 50 MHz */
426#define CFG_MAMR_PTA 98
427#endif /*CONFIG_??MHz */
428
429/*
430 * For 16 MBit, refresh rates could be 31.3 us
431 * (= 64 ms / 2K = 125 / quad bursts).
432 * For a simpler initialization, 15.6 us is used instead.
433 *
434 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
435 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
436 */
437#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
438#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
439
440/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
441#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
442#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
443
444/*
445 * MAMR settings for SDRAM
446 */
447
448/* 8 column SDRAM */
449#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
450 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
452/* 9 column SDRAM */
453#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
454 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
456
457
458/*
459 * Internal Definitions
460 *
461 * Boot Flags
462 */
463#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
464#define BOOTFLAG_WARM 0x02 /* Software reboot */
465
466#undef CONFIG_SCC1_ENET
467#define CONFIG_FEC_ENET
468/* #define CONFIG_ETHPRIME "FEC ETHERNET" */
469
470#endif /* __CONFIG_H */