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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roeseb0f80b92015-01-19 11:33:42 +01002/*
Stefan Roesea5f88872016-01-07 14:09:09 +01003 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roeseb0f80b92015-01-19 11:33:42 +01004 */
5
6#include <common.h>
Stefan Roese64512232015-11-25 07:37:00 +01007#include <dm.h>
8#include <debug_uart.h>
9#include <fdtdec.h>
Stefan Roeseb0f80b92015-01-19 11:33:42 +010010#include <spl.h>
11#include <asm/io.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/soc.h>
14
Stefan Roesea5f88872016-01-07 14:09:09 +010015static u32 get_boot_device(void)
16{
17 u32 val;
18 u32 boot_device;
19
Stefan Roesef4db6c92016-01-07 14:12:04 +010020 /*
21 * First check, if UART boot-mode is active. This can only
22 * be done, via the bootrom error register. Here the
23 * MSB marks if the UART mode is active.
24 */
25 val = readl(CONFIG_BOOTROM_ERR_REG);
26 boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
27 debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
28 if (boot_device == BOOTROM_ERR_MODE_UART)
29 return BOOT_DEVICE_UART;
30
Chris Packham2fd42842018-08-17 20:47:42 +120031#ifdef CONFIG_ARMADA_38X
32 /*
33 * If the bootrom error code contains any other than zeros it's an
34 * error condition and the bootROM has fallen back to UART boot
35 */
36 boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
37 if (boot_device)
38 return BOOT_DEVICE_UART;
39#endif
40
Stefan Roesef4db6c92016-01-07 14:12:04 +010041 /*
42 * Now check the SAR register for the strapped boot-device
43 */
Stefan Roesea5f88872016-01-07 14:09:09 +010044 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
45 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
Stefan Roesef4db6c92016-01-07 14:12:04 +010046 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
Stefan Roesea5f88872016-01-07 14:09:09 +010047 switch (boot_device) {
Sean Nyekjaer926c8b22017-11-24 14:01:47 +010048#if defined(CONFIG_ARMADA_38X)
49 case BOOT_FROM_NAND:
50 return BOOT_DEVICE_NAND;
51#endif
Stefan Roesea5f88872016-01-07 14:09:09 +010052#ifdef CONFIG_SPL_MMC_SUPPORT
53 case BOOT_FROM_MMC:
54 case BOOT_FROM_MMC_ALT:
55 return BOOT_DEVICE_MMC1;
56#endif
57 case BOOT_FROM_UART:
Baruch Siachf3a88e22017-09-24 15:50:17 +030058#ifdef BOOT_FROM_UART_ALT
59 case BOOT_FROM_UART_ALT:
60#endif
Stefan Roesea5f88872016-01-07 14:09:09 +010061 return BOOT_DEVICE_UART;
62 case BOOT_FROM_SPI:
63 default:
64 return BOOT_DEVICE_SPI;
65 };
66}
67
Stefan Roeseb0f80b92015-01-19 11:33:42 +010068u32 spl_boot_device(void)
69{
Stefan Roesea5f88872016-01-07 14:09:09 +010070 return get_boot_device();
Stefan Roeseb0f80b92015-01-19 11:33:42 +010071}
72
73void board_init_f(ulong dummy)
74{
Stefan Roese64512232015-11-25 07:37:00 +010075 int ret;
76
Stefan Roesee3cccf92015-04-17 18:13:06 +020077 /*
78 * Pin muxing needs to be done before UART output, since
79 * on A38x the UART pins need some re-muxing for output
80 * to work.
81 */
82 board_early_init_f();
83
Stefan Roese64512232015-11-25 07:37:00 +010084 /* Example code showing how to enable the debug UART on MVEBU */
85#ifdef EARLY_UART
86 /*
87 * Debug UART can be used from here if required:
88 *
89 * debug_uart_init();
90 * printch('a');
91 * printhex8(0x1234);
92 * printascii("string");
93 */
94#endif
95
Stefan Roesef2100f62019-04-12 16:42:28 +020096 /*
97 * Use special translation offset for SPL. This needs to be
98 * configured *before* spl_init() is called as this function
99 * calls dm_init() which calls the bind functions of the
100 * device drivers. Here the base address needs to be configured
101 * (translated) correctly.
102 */
103 gd->translation_offset = 0xd0000000 - 0xf1000000;
104
Stefan Roese64512232015-11-25 07:37:00 +0100105 ret = spl_init();
106 if (ret) {
107 debug("spl_init() failed: %d\n", ret);
108 hang();
109 }
110
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100111 preloader_console_init();
112
Stefan Roeseade741b2015-07-15 15:36:52 +0200113 timer_init();
114
Stefan Roese09e89ab2016-02-10 07:23:00 +0100115 /* Armada 375 does not support SerDes and DDR3 init yet */
116#if !defined(CONFIG_ARMADA_375)
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100117 /* First init the serdes PHY's */
118 serdes_phy_config();
119
120 /* Setup DDR */
121 ddr3_init();
Stefan Roese09e89ab2016-02-10 07:23:00 +0100122#endif
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100123
Stefan Roese944c7a32015-08-25 13:49:41 +0200124 /*
125 * Return to the BootROM to continue the Marvell xmodem
126 * UART boot protocol. As initiated by the kwboot tool.
127 *
128 * This can only be done by the BootROM and not by the
129 * U-Boot SPL infrastructure, since the beginning of the
130 * image is already read and interpreted by the BootROM.
131 * SPL has no chance to receive this information. So we
132 * need to return to the BootROM to enable this xmodem
133 * UART download.
Sean Nyekjaer926c8b22017-11-24 14:01:47 +0100134 *
135 * If booting from NAND lets let the BootROM load the
136 * rest of the bootloader.
Stefan Roese944c7a32015-08-25 13:49:41 +0200137 */
Sean Nyekjaer926c8b22017-11-24 14:01:47 +0100138 switch (get_boot_device()) {
139 case BOOT_DEVICE_UART:
140#if defined(CONFIG_ARMADA_38X)
141 case BOOT_DEVICE_NAND:
142#endif
143 return_to_bootrom();
144 }
Stefan Roeseb0f80b92015-01-19 11:33:42 +0100145}