blob: c5fe92e06154cd694f08683cc7921b947919a305 [file] [log] [blame]
wdenk8b07a112004-07-10 21:45:47 +00001/*
2 * (C) Copyright 2003,Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
8 * Added support for Wind River SBC8560 board
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29
wdenk8b07a112004-07-10 21:45:47 +000030#include <common.h>
31#include <asm/processor.h>
Kumar Gala8e553132008-08-26 23:52:58 -050032#include <asm/mmu.h>
wdenk8b07a112004-07-10 21:45:47 +000033#include <asm/immap_85xx.h>
Kumar Gala8e553132008-08-26 23:52:58 -050034#include <asm/fsl_ddr_sdram.h>
wdenk8b07a112004-07-10 21:45:47 +000035#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060036#include <spd_sdram.h>
wdenk8b07a112004-07-10 21:45:47 +000037#include <miiphy.h>
Paul Gortmakerd04e76e2008-07-11 15:33:06 -040038#include <libfdt.h>
39#include <fdt_support.h>
wdenk8b07a112004-07-10 21:45:47 +000040
wdenk8b07a112004-07-10 21:45:47 +000041/*
42 * I/O Port configuration table
43 *
44 * if conf is 1, then that port pin will be configured at boot time
45 * according to the five values podr/pdir/ppar/psor/pdat for that entry
46 */
47
48const iop_conf_t iop_conf_tab[4][32] = {
49
50 /* Port A configuration */
51 { /* conf ppar psor pdir podr pdat */
52 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
53 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
54 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
55 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
56 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
57 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
58 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
59 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
60 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
61 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
62 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
63 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
64 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
65 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
66 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
67 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
68 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
69 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
70 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
71 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
72 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
73 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
74 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
75 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
76 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
77 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
78 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
79 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
80 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
81 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
82 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
83 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
84 },
85
86 /* Port B configuration */
87 { /* conf ppar psor pdir podr pdat */
88 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
89 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
90 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
91 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
92 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
93 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
94 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
95 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
96 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
97 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
98 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
99 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
100 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
101 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
102 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
103 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
104 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
105 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
106 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
107 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
108 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
109 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
110 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
113 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
114 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
117 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
120 },
121
122 /* Port C */
123 { /* conf ppar psor pdir podr pdat */
124 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
125 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
126 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
127 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
128 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
129 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
130 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
131 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
132 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
133 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
134 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
135 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
136 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
137 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
138 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
139 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
140 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
141 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
142 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
143 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
144 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
145 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
146 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
147 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
148 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
149 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
150 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
151 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
152 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
153 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
154 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
155 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
156 },
157
158 /* Port D */
159 { /* conf ppar psor pdir podr pdat */
160 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
161 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
162 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
163 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
164 /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
165 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
166 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
167 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
168 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
169 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
170 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
171 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
172 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
173 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
174 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
175 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
176 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
177 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
178 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
179 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
180 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
181 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
182 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
183 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
184 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
185 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
186 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
187 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
188 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
189 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
192 }
193};
194
195int board_early_init_f (void)
196{
197#if defined(CONFIG_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
wdenk8b07a112004-07-10 21:45:47 +0000199
200 pci->peer &= 0xfffffffdf; /* disable master abort */
201#endif
202 return 0;
203}
204
205void reset_phy (void)
206{
207#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
wdenk8b07a112004-07-10 21:45:47 +0000209#endif
210 /* reset Giga bit Ethernet port if needed here */
211
212 /* reset the CPM FEC port */
213#if (CONFIG_ETHER_INDEX == 2)
214 bcsr[0] &= ~0x20;
215 udelay(2);
216 bcsr[0] |= 0x20;
217 udelay(1000);
218#elif (CONFIG_ETHER_INDEX == 3)
219 bcsr[0] &= ~0x10;
220 udelay(2);
221 bcsr[0] |= 0x10;
222 udelay(1000);
223#endif
224#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200225 /* reset PHY */
Heiko Schocher48690d82010-07-20 17:45:02 +0200226 miiphy_reset("FCC1", 0x0);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200227
228 /* change PHY address to 0x02 */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500229 bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200230
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500231 bb_miiphy_write(NULL, 0x02, MII_BMCR,
232 BMCR_ANENABLE | BMCR_ANRESTART);
wdenk8b07a112004-07-10 21:45:47 +0000233#endif /* CONFIG_MII */
234}
235
236int checkboard (void)
237{
238 sys_info_t sysinfo;
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200239 char buf[32];
wdenk8b07a112004-07-10 21:45:47 +0000240
241 get_sys_info (&sysinfo);
242
wdenkc15f3122004-10-10 22:44:24 +0000243#ifdef CONFIG_SBC8560
wdenk8b07a112004-07-10 21:45:47 +0000244 printf ("Board: Wind River SBC8560 Board\n");
wdenkc15f3122004-10-10 22:44:24 +0000245#else
246 printf ("Board: Wind River SBC8540 Board\n");
247#endif
Wolfgang Denk1fbcbe92009-01-28 23:06:42 +0100248 printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200249 printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
250 printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
252 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200253 printf ("\tLBC: %s MHz\n",
254 strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
wdenk8b07a112004-07-10 21:45:47 +0000255 } else {
256 printf("\tLBC: unknown\n");
257 }
Wolfgang Denk08ef89e2008-10-19 02:35:49 +0200258 printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
wdenk8b07a112004-07-10 21:45:47 +0000259 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
260 return (0);
261}
262
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#if defined(CONFIG_SYS_DRAM_TEST)
wdenk8b07a112004-07-10 21:45:47 +0000265int testdram (void)
266{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
268 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
wdenk8b07a112004-07-10 21:45:47 +0000269 uint *p;
270
271 printf("SDRAM test phase 1:\n");
272 for (p = pstart; p < pend; p++)
273 *p = 0xaaaaaaaa;
274
275 for (p = pstart; p < pend; p++) {
276 if (*p != 0xaaaaaaaa) {
277 printf ("SDRAM test fails at: %08x\n", (uint) p);
278 return 1;
279 }
280 }
281
282 printf("SDRAM test phase 2:\n");
283 for (p = pstart; p < pend; p++)
284 *p = 0x55555555;
285
286 for (p = pstart; p < pend; p++) {
287 if (*p != 0x55555555) {
288 printf ("SDRAM test fails at: %08x\n", (uint) p);
289 return 1;
290 }
291 }
292
293 printf("SDRAM test passed.\n");
294 return 0;
295}
296#endif
297
298#if !defined(CONFIG_SPD_EEPROM)
299/*************************************************************************
300 * fixed sdram init -- doesn't use serial presence detect.
301 ************************************************************************/
Becky Bruce38dba0c2010-12-17 17:17:56 -0600302phys_size_t fixed_sdram(void)
wdenk8b07a112004-07-10 21:45:47 +0000303{
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_DDR_CONTROL 0xc2000000
wdenk8b07a112004-07-10 21:45:47 +0000306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 #ifndef CONFIG_SYS_RAMBOOT
308 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
wdenk8b07a112004-07-10 21:45:47 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#if (CONFIG_SYS_SDRAM_SIZE == 512)
Paul Gortmaker0ec436d2008-07-11 15:33:04 -0400311 ddr->cs0_bnds = 0x0000000f;
312#else
wdenk8b07a112004-07-10 21:45:47 +0000313 ddr->cs0_bnds = 0x00000007;
Paul Gortmaker0ec436d2008-07-11 15:33:04 -0400314#endif
wdenk8b07a112004-07-10 21:45:47 +0000315 ddr->cs1_bnds = 0x0010001f;
316 ddr->cs2_bnds = 0x00000000;
317 ddr->cs3_bnds = 0x00000000;
318 ddr->cs0_config = 0x80000102;
319 ddr->cs1_config = 0x80000102;
320 ddr->cs2_config = 0x00000000;
321 ddr->cs3_config = 0x00000000;
322 ddr->timing_cfg_1 = 0x37334321;
323 ddr->timing_cfg_2 = 0x00000800;
324 ddr->sdram_cfg = 0x42000000;
325 ddr->sdram_mode = 0x00000022;
326 ddr->sdram_interval = 0x05200100;
327 ddr->err_sbe = 0x00ff0000;
328 #if defined (CONFIG_DDR_ECC)
329 ddr->err_disable = 0x0000000D;
330 #endif
331 asm("sync;isync;msync");
332 udelay(500);
333 #if defined (CONFIG_DDR_ECC)
334 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
wdenk8b07a112004-07-10 21:45:47 +0000336 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
wdenk8b07a112004-07-10 21:45:47 +0000338 #endif
339 asm("sync; isync; msync");
340 udelay(500);
341 #endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
wdenk8b07a112004-07-10 21:45:47 +0000343}
344#endif /* !defined(CONFIG_SPD_EEPROM) */
Paul Gortmakerd04e76e2008-07-11 15:33:06 -0400345
346
347#if defined(CONFIG_OF_BOARD_SETUP)
348void
349ft_board_setup(void *blob, bd_t *bd)
350{
351 int node, tmp[2];
352#ifdef CONFIG_PCI
353 const char *path;
354#endif
355
356 ft_cpu_setup(blob, bd);
357
358 node = fdt_path_offset(blob, "/aliases");
359 tmp[0] = 0;
360 if (node >= 0) {
361#ifdef CONFIG_PCI
362 path = fdt_getprop(blob, node, "pci0", NULL);
363 if (path) {
364 tmp[1] = hose.last_busno - hose.first_busno;
365 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
366 }
367#endif
368 }
369}
370#endif