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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b867d705b6217fed505dd44cf539699b8a81733d / . / include / pci.h
blob: e5055b175340a26a1393f267d37740b197deeb44 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * aloong with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef _PCI_H
28#define _PCI_H
29
30/*
31 * Under PCI, each device has 256 bytes of configuration address space,
32 * of which the first 64 bytes are standardized as follows:
33 */
34#define PCI_VENDOR_ID 0x00 /* 16 bits */
35#define PCI_DEVICE_ID 0x02 /* 16 bits */
36#define PCI_COMMAND 0x04 /* 16 bits */
37#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
38#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
39#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
40#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
41#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
42#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
43#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
44#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
45#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
46#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
47
48#define PCI_STATUS 0x06 /* 16 bits */
49#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
50#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
51#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
52#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
53#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
54#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
55#define PCI_STATUS_DEVSEL_FAST 0x000
56#define PCI_STATUS_DEVSEL_MEDIUM 0x200
57#define PCI_STATUS_DEVSEL_SLOW 0x400
58#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
59#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
60#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
61#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
62#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
63
64#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
65 revision */
66#define PCI_REVISION_ID 0x08 /* Revision ID */
67#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
68#define PCI_CLASS_DEVICE 0x0a /* Device class */
69#define PCI_CLASS_CODE 0x0b /* Device class code */
70#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
71
72#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
73#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
74#define PCI_HEADER_TYPE 0x0e /* 8 bits */
75#define PCI_HEADER_TYPE_NORMAL 0
76#define PCI_HEADER_TYPE_BRIDGE 1
77#define PCI_HEADER_TYPE_CARDBUS 2
78
79#define PCI_BIST 0x0f /* 8 bits */
80#define PCI_BIST_CODE_MASK 0x0f /* Return result */
81#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
82#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
83
84/*
85 * Base addresses specify locations in memory or I/O space.
86 * Decoded size can be determined by writing a value of
87 * 0xffffffff to the register, and reading it back. Only
88 * 1 bits are decoded.
89 */
90#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
91#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
92#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
93#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
94#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
95#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
96#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
97#define PCI_BASE_ADDRESS_SPACE_IO 0x01
98#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
99#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
100#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
101#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
102#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
103#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
104#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
105#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
106/* bit 1 is reserved if address_space = 1 */
107
108/* Header type 0 (normal devices) */
109#define PCI_CARDBUS_CIS 0x28
110#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
111#define PCI_SUBSYSTEM_ID 0x2e
112#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
113#define PCI_ROM_ADDRESS_ENABLE 0x01
114#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
115
116#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
117
118/* 0x35-0x3b are reserved */
119#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
120#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
121#define PCI_MIN_GNT 0x3e /* 8 bits */
122#define PCI_MAX_LAT 0x3f /* 8 bits */
123
124/* Header type 1 (PCI-to-PCI bridges) */
125#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
126#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
127#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
128#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
129#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
130#define PCI_IO_LIMIT 0x1d
131#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
132#define PCI_IO_RANGE_TYPE_16 0x00
133#define PCI_IO_RANGE_TYPE_32 0x01
134#define PCI_IO_RANGE_MASK ~0x0f
135#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
136#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
137#define PCI_MEMORY_LIMIT 0x22
138#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
139#define PCI_MEMORY_RANGE_MASK ~0x0f
140#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
141#define PCI_PREF_MEMORY_LIMIT 0x26
142#define PCI_PREF_RANGE_TYPE_MASK 0x0f
143#define PCI_PREF_RANGE_TYPE_32 0x00
144#define PCI_PREF_RANGE_TYPE_64 0x01
145#define PCI_PREF_RANGE_MASK ~0x0f
146#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
147#define PCI_PREF_LIMIT_UPPER32 0x2c
148#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
149#define PCI_IO_LIMIT_UPPER16 0x32
150/* 0x34 same as for htype 0 */
151/* 0x35-0x3b is reserved */
152#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
153/* 0x3c-0x3d are same as for htype 0 */
154#define PCI_BRIDGE_CONTROL 0x3e
155#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
156#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
157#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
158#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
159#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
160#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
161#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
162
163/* Header type 2 (CardBus bridges) */
164#define PCI_CB_CAPABILITY_LIST 0x14
165/* 0x15 reserved */
166#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
167#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
168#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
169#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
170#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
171#define PCI_CB_MEMORY_BASE_0 0x1c
172#define PCI_CB_MEMORY_LIMIT_0 0x20
173#define PCI_CB_MEMORY_BASE_1 0x24
174#define PCI_CB_MEMORY_LIMIT_1 0x28
175#define PCI_CB_IO_BASE_0 0x2c
176#define PCI_CB_IO_BASE_0_HI 0x2e
177#define PCI_CB_IO_LIMIT_0 0x30
178#define PCI_CB_IO_LIMIT_0_HI 0x32
179#define PCI_CB_IO_BASE_1 0x34
180#define PCI_CB_IO_BASE_1_HI 0x36
181#define PCI_CB_IO_LIMIT_1 0x38
182#define PCI_CB_IO_LIMIT_1_HI 0x3a
183#define PCI_CB_IO_RANGE_MASK ~0x03
184/* 0x3c-0x3d are same as for htype 0 */
185#define PCI_CB_BRIDGE_CONTROL 0x3e
186#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
187#define PCI_CB_BRIDGE_CTL_SERR 0x02
188#define PCI_CB_BRIDGE_CTL_ISA 0x04
189#define PCI_CB_BRIDGE_CTL_VGA 0x08
190#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
191#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
192#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
193#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
194#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
195#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
196#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
197#define PCI_CB_SUBSYSTEM_ID 0x42
198#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
199/* 0x48-0x7f reserved */
200
201/* Capability lists */
202
203#define PCI_CAP_LIST_ID 0 /* Capability ID */
204#define PCI_CAP_ID_PM 0x01 /* Power Management */
205#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
206#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
207#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
208#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
209#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
210#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
211#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
212#define PCI_CAP_SIZEOF 4
213
214/* Power Management Registers */
215
216#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
217#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
218#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
219#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
220#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
221#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
222#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
223#define PCI_PM_CTRL 4 /* PM control and status register */
224#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
225#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
226#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
227#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
228#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
229#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
230#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
231#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
232#define PCI_PM_DATA_REGISTER 7 /* (??) */
233#define PCI_PM_SIZEOF 8
234
235/* AGP registers */
236
237#define PCI_AGP_VERSION 2 /* BCD version number */
238#define PCI_AGP_RFU 3 /* Rest of capability flags */
239#define PCI_AGP_STATUS 4 /* Status register */
240#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
241#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
242#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
243#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
244#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
245#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
246#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
247#define PCI_AGP_COMMAND 8 /* Control register */
248#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
249#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
250#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
251#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
252#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
253#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
254#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
255#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
256#define PCI_AGP_SIZEOF 12
257
258/* Slot Identification */
259
260#define PCI_SID_ESR 2 /* Expansion Slot Register */
261#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
262#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
263#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
264
265/* Message Signalled Interrupts registers */
266
267#define PCI_MSI_FLAGS 2 /* Various flags */
268#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
269#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
270#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
271#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
272#define PCI_MSI_RFU 3 /* Rest of capability flags */
273#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
274#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
275#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
276#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
277
278#define PCI_MAX_PCI_DEVICES 32
279#define PCI_MAX_PCI_FUNCTIONS 8
280
281/* Include the ID list */
282
283#include <pci_ids.h>
284
285struct pci_region {
286 unsigned long bus_start; /* Start on the bus */
287 unsigned long phys_start; /* Start in physical address space */
288 unsigned long size; /* Size */
289 unsigned long flags; /* Resource flags */
290
291 unsigned long bus_lower;
292};
293
294#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
295#define PCI_REGION_IO 0x00000001 /* PCI IO space */
296#define PCI_REGION_TYPE 0x00000001
297
298#define PCI_REGION_MEMORY 0x00000100 /* System memory */
299#define PCI_REGION_RO 0x00000200 /* Read-only memory */
300
301extern __inline__ void pci_set_region(struct pci_region *reg,
302 unsigned long bus_start,
303 unsigned long phys_start,
304 unsigned long size,
305 unsigned long flags) {
306 reg->bus_start = bus_start;
307 reg->phys_start = phys_start;
308 reg->size = size;
309 reg->flags = flags;
310}
311
312typedef int pci_dev_t;
313
314#define PCI_BUS(d) (((d) >> 16) & 0xff)
315#define PCI_DEV(d) (((d) >> 11) & 0x1f)
316#define PCI_FUNC(d) (((d) >> 8) & 0x7)
317#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
318
319#define PCI_ANY_ID (~0)
320
321struct pci_device_id {
322 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
323};
324
325struct pci_controller;
326
327struct pci_config_table {
328 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
329 unsigned int class; /* Class ID, or PCI_ANY_ID */
330 unsigned int bus; /* Bus number, or PCI_ANY_ID */
331 unsigned int dev; /* Device number, or PCI_ANY_ID */
332 unsigned int func; /* Function number, or PCI_ANY_ID */
333
334 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
335 struct pci_config_table *);
336 unsigned long priv[3];
337};
338
339extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
340 struct pci_config_table *);
341extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
342 struct pci_config_table *);
343
344#define MAX_PCI_REGIONS 7
345
346/*
347 * Structure of a PCI controller (host bridge)
348 */
349struct pci_controller {
350 struct pci_controller *next;
351
352 int first_busno;
353 int last_busno;
354
355 volatile unsigned int *cfg_addr;
356 volatile unsigned char *cfg_data;
357
358 struct pci_region regions[MAX_PCI_REGIONS];
359 int region_count;
360
361 struct pci_config_table *config_table;
362
363 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
364
365 /* Low-level architecture-dependent routines */
366 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
367 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
368 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
369 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
370 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
371 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
372
373 /* Used by auto config */
374 struct pci_region *pci_mem, *pci_io;
375
376 /* Used by ppc405 autoconfig*/
377 struct pci_region *pci_fb;
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]378 int current_busno;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]379};
380
381extern __inline__ void pci_set_ops(struct pci_controller *hose,
382 int (*read_byte)(struct pci_controller*,
383 pci_dev_t, int where, u8 *),
384 int (*read_word)(struct pci_controller*,
385 pci_dev_t, int where, u16 *),
386 int (*read_dword)(struct pci_controller*,
387 pci_dev_t, int where, u32 *),
388 int (*write_byte)(struct pci_controller*,
389 pci_dev_t, int where, u8),
390 int (*write_word)(struct pci_controller*,
391 pci_dev_t, int where, u16),
392 int (*write_dword)(struct pci_controller*,
393 pci_dev_t, int where, u32)) {
394 hose->read_byte = read_byte;
395 hose->read_word = read_word;
396 hose->read_dword = read_dword;
397 hose->write_byte = write_byte;
398 hose->write_word = write_word;
399 hose->write_dword = write_dword;
400}
401
402extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
403
404extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
405 unsigned long addr, unsigned long flags);
406extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
407 unsigned long addr, unsigned long flags);
408
409#define pci_phys_to_bus(dev, addr, flags) \
410 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
411#define pci_bus_to_phys(dev, addr, flags) \
412 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
413
414#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
415#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
416#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
417#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
418
419extern int pci_hose_read_config_byte(struct pci_controller *hose,
420 pci_dev_t dev, int where, u8 *val);
421extern int pci_hose_read_config_word(struct pci_controller *hose,
422 pci_dev_t dev, int where, u16 *val);
423extern int pci_hose_read_config_dword(struct pci_controller *hose,
424 pci_dev_t dev, int where, u32 *val);
425extern int pci_hose_write_config_byte(struct pci_controller *hose,
426 pci_dev_t dev, int where, u8 val);
427extern int pci_hose_write_config_word(struct pci_controller *hose,
428 pci_dev_t dev, int where, u16 val);
429extern int pci_hose_write_config_dword(struct pci_controller *hose,
430 pci_dev_t dev, int where, u32 val);
431
432extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
433extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
434extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
435extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
436extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
437extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
438
439extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
440 pci_dev_t dev, int where, u8 *val);
441extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
442 pci_dev_t dev, int where, u16 *val);
443extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
444 pci_dev_t dev, int where, u8 val);
445extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
446 pci_dev_t dev, int where, u16 val);
447
448extern void pci_register_hose(struct pci_controller* hose);
449extern struct pci_controller* pci_bus_to_hose(int bus);
450
451extern int pci_hose_scan(struct pci_controller *hose);
452extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
453
454extern void pciauto_region_init(struct pci_region* res);
455extern void pciauto_region_align(struct pci_region *res, unsigned long size);
456extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
457extern void pciauto_setup_device(struct pci_controller *hose,
458 pci_dev_t dev, int bars_num,
459 struct pci_region *mem,
460 struct pci_region *io);
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]461int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]462
463extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
464extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
465
466extern int pci_hose_config_device(struct pci_controller *hose,
467 pci_dev_t dev,
468 unsigned long io,
469 unsigned long mem,
470 unsigned long command);
471
472#ifdef CONFIG_MPC824X
473extern void pci_mpc824x_init (struct pci_controller *hose);
474#endif
475
476#endif /* _PCI_H */