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wdenkba56f622004-02-06 23:19:44 +00001/*
Peter Tysere0299072009-07-17 19:01:07 -05002 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
wdenkba56f622004-02-06 23:19:44 +00003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Peter Tysere0299072009-07-17 19:01:07 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkba56f622004-02-06 23:19:44 +000015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
wdenkba56f622004-02-06 23:19:44 +000023#include <common.h>
24#include <asm/processor.h>
25#include <spd_sdram.h>
26#include <i2c.h>
Wolfgang Denkd2567be2009-03-28 20:16:16 +010027#include <net.h>
wdenkba56f622004-02-06 23:19:44 +000028
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
30
wdenk3c74e322004-02-22 23:46:08 +000031int board_early_init_f(void)
wdenkba56f622004-02-06 23:19:44 +000032{
33 unsigned long sdrreg;
Peter Tysere0299072009-07-17 19:01:07 -050034
Peter Tyserb88da152009-07-17 19:01:09 -050035 /*
36 * Enable GPIO for pins 18 - 24
37 * 18 = SEEPROM_WP
38 * 19 = #M_RST
39 * 20 = #MONARCH
40 * 21 = #LED_ALARM
41 * 22 = #LED_ACT
42 * 23 = #LED_STATUS1
43 * 24 = #LED_STATUS2
44 */
wdenkba56f622004-02-06 23:19:44 +000045 mfsdr(sdr_pfc0, sdrreg);
Peter Tyserb88da152009-07-17 19:01:09 -050046 mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
wdenkba56f622004-02-06 23:19:44 +000048 LED0_OFF();
49 LED1_OFF();
50 LED2_OFF();
51 LED3_OFF();
52
Peter Tysere0299072009-07-17 19:01:07 -050053 /* Setup the external bus controller/chip selects */
54 mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
55 mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
56 mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
57 mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
Peter Tyser42735812009-07-17 19:01:08 -050058 mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
59 mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
60 mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
61 mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
wdenkba56f622004-02-06 23:19:44 +000062
Stefan Roese5de85142008-06-26 17:36:39 +020063 /*
Peter Tysere0299072009-07-17 19:01:07 -050064 * Setup the interrupt controller polarities, triggers, etc.
65 *
Stefan Roese5de85142008-06-26 17:36:39 +020066 * Because of the interrupt handling rework to handle 440GX interrupts
67 * with the common code, we needed to change names of the UIC registers.
68 * Here the new relationship:
69 *
70 * U-Boot name 440GX name
71 * -----------------------
72 * UIC0 UICB0
73 * UIC1 UIC0
74 * UIC2 UIC1
75 * UIC3 UIC2
76 */
Peter Tysere0299072009-07-17 19:01:07 -050077 mtdcr(uic1sr, 0xffffffff); /* clear all */
78 mtdcr(uic1er, 0x00000000); /* disable all */
79 mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
80 mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
81 mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
82 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
83 mtdcr(uic1sr, 0xffffffff); /* clear all */
wdenkba56f622004-02-06 23:19:44 +000084
Peter Tysere0299072009-07-17 19:01:07 -050085 mtdcr(uic2sr, 0xffffffff); /* clear all */
86 mtdcr(uic2er, 0x00000000); /* disable all */
87 mtdcr(uic2cr, 0x00000000); /* all non-critical */
88 mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
89 mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
90 mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
91 mtdcr(uic2sr, 0xffffffff); /* clear all */
wdenkba56f622004-02-06 23:19:44 +000092
Peter Tysere0299072009-07-17 19:01:07 -050093 mtdcr(uic3sr, 0xffffffff); /* clear all */
94 mtdcr(uic3er, 0x00000000); /* disable all */
95 mtdcr(uic3cr, 0x00000000); /* all non-critical */
96 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
97 mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
98 mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
99 mtdcr(uic3sr, 0xffffffff); /* clear all */
Stefan Roese5de85142008-06-26 17:36:39 +0200100
Peter Tysere0299072009-07-17 19:01:07 -0500101 mtdcr(uic0sr, 0xfc000000); /* clear all */
102 mtdcr(uic0er, 0x00000000); /* disable all */
103 mtdcr(uic0cr, 0x00000000); /* all non-critical */
104 mtdcr(uic0pr, 0xfc000000); /* */
105 mtdcr(uic0tr, 0x00000000); /* */
106 mtdcr(uic0vr, 0x00000001); /* */
wdenkba56f622004-02-06 23:19:44 +0000107
108 LED0_ON();
109
wdenkba56f622004-02-06 23:19:44 +0000110 return 0;
111}
112
Peter Tysere0299072009-07-17 19:01:07 -0500113int checkboard(void)
wdenkba56f622004-02-06 23:19:44 +0000114{
Peter Tysere0299072009-07-17 19:01:07 -0500115 printf("Board: XES XPedite1000 440GX\n");
wdenkba56f622004-02-06 23:19:44 +0000116
Peter Tysere0299072009-07-17 19:01:07 -0500117 return 0;
wdenkba56f622004-02-06 23:19:44 +0000118}
119
Peter Tysere0299072009-07-17 19:01:07 -0500120phys_size_t initdram(int board_type)
wdenkba56f622004-02-06 23:19:44 +0000121{
Peter Tyser108d6d02009-07-17 19:01:05 -0500122 return spd_sdram();
wdenkba56f622004-02-06 23:19:44 +0000123}
124
Peter Tysere0299072009-07-17 19:01:07 -0500125/*
126 * This routine is called just prior to registering the hose and gives
127 * the board the opportunity to check things. Returning a value of zero
128 * indicates that things are bad & PCI initialization should be aborted.
129 *
130 * Different boards may wish to customize the pci controller structure
131 * (add regions, override default access routines, etc) or perform
132 * certain pre-initialization actions.
133 */
wdenkba56f622004-02-06 23:19:44 +0000134
Stefan Roese466fff12007-06-25 15:57:39 +0200135#if defined(CONFIG_PCI)
Peter Tysere0299072009-07-17 19:01:07 -0500136int pci_pre_init(struct pci_controller * hose)
wdenkba56f622004-02-06 23:19:44 +0000137{
138 unsigned long strap;
Peter Tysere0299072009-07-17 19:01:07 -0500139
wdenk3c74e322004-02-22 23:46:08 +0000140 /* See if we're supposed to setup the pci */
141 mfsdr(sdr_sdstp1, strap);
Peter Tysere0299072009-07-17 19:01:07 -0500142 if ((strap & 0x00010000) == 0)
143 return 0;
wdenkba56f622004-02-06 23:19:44 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
wdenk3c74e322004-02-22 23:46:08 +0000146 /* Setup System Device Register PCIX0_XCR */
147 mfsdr(sdr_xcr, strap);
148 strap &= 0x0f000000;
149 mtsdr(sdr_xcr, strap);
150#endif
Peter Tysere0299072009-07-17 19:01:07 -0500151
wdenkba56f622004-02-06 23:19:44 +0000152 return 1;
153}
Stefan Roese466fff12007-06-25 15:57:39 +0200154#endif /* defined(CONFIG_PCI) */
wdenkba56f622004-02-06 23:19:44 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Peter Tysere0299072009-07-17 19:01:07 -0500157/*
158 * The bootstrap configuration provides default settings for the pci
159 * inbound map (PIM). But the bootstrap config choices are limited and
160 * may not be sufficient for a given board.
161 */
162void pci_target_init(struct pci_controller * hose)
wdenkba56f622004-02-06 23:19:44 +0000163{
Peter Tysere0299072009-07-17 19:01:07 -0500164 /* Disable everything */
165 out32r(PCIX0_PIM0SA, 0);
166 out32r(PCIX0_PIM1SA, 0);
167 out32r(PCIX0_PIM2SA, 0);
168 out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
wdenkba56f622004-02-06 23:19:44 +0000169
Peter Tysere0299072009-07-17 19:01:07 -0500170 /*
wdenkba56f622004-02-06 23:19:44 +0000171 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
172 * options to not support sizes such as 128/256 MB.
Peter Tysere0299072009-07-17 19:01:07 -0500173 */
174 out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
175 out32r(PCIX0_PIM0LAH, 0);
176 out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
wdenkba56f622004-02-06 23:19:44 +0000177
Peter Tysere0299072009-07-17 19:01:07 -0500178 out32r(PCIX0_BAR0, 0);
wdenkba56f622004-02-06 23:19:44 +0000179
Peter Tysere0299072009-07-17 19:01:07 -0500180 /* Program the board's subsystem id/vendor id */
181 out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
182 out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
wdenkba56f622004-02-06 23:19:44 +0000183
Peter Tysere0299072009-07-17 19:01:07 -0500184 out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
wdenkba56f622004-02-06 23:19:44 +0000185}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
wdenkba56f622004-02-06 23:19:44 +0000187
wdenkba56f622004-02-06 23:19:44 +0000188#if defined(CONFIG_PCI)
Peter Tysere0299072009-07-17 19:01:07 -0500189/*
190 * This routine is called to determine if a pci scan should be
191 * performed. With various hardware environments (especially cPCI and
192 * PPMC) it's insufficient to depend on the state of the arbiter enable
193 * bit in the strap register, or generic host/adapter assumptions.
194 *
195 * Rather than hard-code a bad assumption in the general 440 code, the
196 * 440 pci code requires the board to decide at runtime.
197 *
198 * Return 0 for adapter mode, non-zero for host (monarch) mode.
199 */
wdenkba56f622004-02-06 23:19:44 +0000200int is_pci_host(struct pci_controller *hose)
201{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
wdenkba56f622004-02-06 23:19:44 +0000203}
204#endif /* defined(CONFIG_PCI) */
205
206#ifdef CONFIG_POST
207/*
208 * Returns 1 if keys pressed to start the power-on long-running tests
209 * Called from board_init_f().
210 */
211int post_hotkeys_pressed(void)
212{
Peter Tysere0299072009-07-17 19:01:07 -0500213 return ctrlc();
wdenkba56f622004-02-06 23:19:44 +0000214}
215
Peter Tysere0299072009-07-17 19:01:07 -0500216void post_word_store(ulong a)
wdenkba56f622004-02-06 23:19:44 +0000217{
218 volatile ulong *save_addr =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
wdenkba56f622004-02-06 23:19:44 +0000220
221 *save_addr = a;
222}
223
Peter Tysere0299072009-07-17 19:01:07 -0500224ulong post_word_load(void)
wdenkba56f622004-02-06 23:19:44 +0000225{
226 volatile ulong *save_addr =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
wdenkba56f622004-02-06 23:19:44 +0000228
229 return *save_addr;
230}
Peter Tysere0299072009-07-17 19:01:07 -0500231#endif