| Neil Armstrong | 485bba3 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 4 | * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/arch/eth.h> |
| 9 | #include <asm/arch/axg.h> |
| 10 | #include <asm/arch/mem.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/armv8/mmu.h> |
| 13 | #include <linux/sizes.h> |
| 14 | #include <phy.h> |
| 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | /* Configure the reserved memory zones exported by the secure registers |
| 19 | * into EFI and DTB reserved memory entries. |
| 20 | */ |
| 21 | void meson_init_reserved_memory(void *fdt) |
| 22 | { |
| 23 | u64 bl31_size, bl31_start; |
| 24 | u64 bl32_size, bl32_start; |
| 25 | u32 reg; |
| 26 | |
| 27 | /* |
| 28 | * Get ARM Trusted Firmware reserved memory zones in : |
| 29 | * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 |
| 30 | * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL |
| 31 | * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL |
| 32 | */ |
| 33 | reg = readl(AXG_AO_SEC_GP_CFG3); |
| 34 | |
| 35 | bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK) |
| 36 | >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; |
| 37 | bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; |
| 38 | |
| 39 | bl31_start = readl(AXG_AO_SEC_GP_CFG5); |
| 40 | bl32_start = readl(AXG_AO_SEC_GP_CFG4); |
| 41 | |
| 42 | /* Add BL31 reserved zone */ |
| 43 | if (bl31_start && bl31_size) |
| 44 | meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); |
| 45 | |
| 46 | /* Add BL32 reserved zone */ |
| 47 | if (bl32_start && bl32_size) |
| 48 | meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); |
| 49 | } |
| 50 | |
| 51 | phys_size_t get_effective_memsize(void) |
| 52 | { |
| 53 | /* Size is reported in MiB, convert it in bytes */ |
| 54 | return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK) |
| 55 | >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M; |
| 56 | } |
| 57 | |
| 58 | static struct mm_region axg_mem_map[] = { |
| 59 | { |
| 60 | .virt = 0x0UL, |
| 61 | .phys = 0x0UL, |
| 62 | .size = 0x80000000UL, |
| 63 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 64 | PTE_BLOCK_INNER_SHARE |
| 65 | }, { |
| 66 | .virt = 0xf0000000UL, |
| 67 | .phys = 0xf0000000UL, |
| 68 | .size = 0x10000000UL, |
| 69 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 70 | PTE_BLOCK_NON_SHARE | |
| 71 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 72 | }, { |
| 73 | /* List terminator */ |
| 74 | 0, |
| 75 | } |
| 76 | }; |
| 77 | |
| 78 | struct mm_region *mem_map = axg_mem_map; |
| 79 | |
| 80 | /* Configure the Ethernet MAC with the requested interface mode |
| 81 | * with some optional flags. |
| 82 | */ |
| 83 | void meson_eth_init(phy_interface_t mode, unsigned int flags) |
| 84 | { |
| 85 | switch (mode) { |
| 86 | case PHY_INTERFACE_MODE_RGMII: |
| 87 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 88 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 89 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 90 | /* Set RGMII mode */ |
| 91 | setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | |
| 92 | AXG_ETH_REG_0_TX_PHASE(1) | |
| 93 | AXG_ETH_REG_0_TX_RATIO(4) | |
| 94 | AXG_ETH_REG_0_PHY_CLK_EN | |
| 95 | AXG_ETH_REG_0_CLK_EN); |
| 96 | break; |
| 97 | |
| 98 | case PHY_INTERFACE_MODE_RMII: |
| 99 | /* Set RMII mode */ |
| 100 | out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | |
| 101 | AXG_ETH_REG_0_INVERT_RMII_CLK | |
| 102 | AXG_ETH_REG_0_CLK_EN); |
| 103 | break; |
| 104 | |
| 105 | default: |
| 106 | printf("Invalid Ethernet interface mode\n"); |
| 107 | return; |
| 108 | } |
| 109 | |
| 110 | /* Enable power gate */ |
| 111 | clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); |
| 112 | } |