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Daniel Hellstromc2f02da2008-03-28 09:47:00 +01001/* psr.h: This file holds the macros for masking off various parts of
2 * the processor status register on the Sparc. This is valid
3 * for Version 8. On the V9 this is renamed to the PSTATE
4 * register and its members are accessed as fields like
5 * PSTATE.PRIV for the current CPU privilege level.
6 *
7 * taken from the SPARC port of Linux,
8 *
9 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
10 * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29#ifndef __SPARC_PSR_H__
30#define __SPARC_PSR_H__
31
32/* The Sparc PSR fields are laid out as the following:
33 *
34 * ------------------------------------------------------------------------
35 * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
36 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
37 * ------------------------------------------------------------------------
38 */
39#define PSR_CWP 0x0000001f /* current window pointer */
40#define PSR_ET 0x00000020 /* enable traps field */
41#define PSR_PS 0x00000040 /* previous privilege level */
42#define PSR_S 0x00000080 /* current privilege level */
43#define PSR_PIL 0x00000f00 /* processor interrupt level */
44#define PSR_EF 0x00001000 /* enable floating point */
45#define PSR_EC 0x00002000 /* enable co-processor */
46#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
47#define PSR_ICC 0x00f00000 /* integer condition codes */
48#define PSR_C 0x00100000 /* carry bit */
49#define PSR_V 0x00200000 /* overflow bit */
50#define PSR_Z 0x00400000 /* zero bit */
51#define PSR_N 0x00800000 /* negative bit */
52#define PSR_VERS 0x0f000000 /* cpu-version field */
53#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
54
55#define PSR_PIL_OFS 8
56
57#ifndef __ASSEMBLY__
58/* Get the %psr register. */
59extern __inline__ unsigned int get_psr(void)
60{
61 unsigned int psr;
62 __asm__ __volatile__("rd %%psr, %0\n\t"
63 "nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr)
64 : /* no inputs */
65 :"memory");
66
67 return psr;
68}
69
70extern __inline__ void put_psr(unsigned int new_psr)
71{
72 __asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */
73 :"r"(new_psr)
74 :"memory", "cc");
75}
76
77/* Get the %fsr register. Be careful, make sure the floating point
78 * enable bit is set in the %psr when you execute this or you will
79 * incur a trap.
80 */
81
82extern unsigned int fsr_storage;
83
84extern __inline__ unsigned int get_fsr(void)
85{
86 unsigned int fsr = 0;
87
88 __asm__ __volatile__("st %%fsr, %1\n\t"
89 "ld %1, %0\n\t":"=r"(fsr)
90 :"m"(fsr_storage));
91
92 return fsr;
93}
94
95#endif /* !(__ASSEMBLY__) */
96
97#endif /* !(__SPARC_PSR_H__) */