blob: 221054593ef221abb9e05e779a9cf18f3b1b5399 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
wdenkf07771c2003-05-28 08:06:31 +00006 * (C) Copyright 2002, 2003
wdenkc6097192002-11-03 00:24:07 +00007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10/*
Simon Glass2b81e8a2015-11-29 13:17:46 -070011 * Old PCI routines
12 *
13 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
14 * and change pci-uclass.c.
wdenkc6097192002-11-03 00:24:07 +000015 */
16
17#include <common.h>
18
wdenkc6097192002-11-03 00:24:07 +000019#include <command.h>
Simon Glass250e0392015-01-27 22:13:27 -070020#include <errno.h>
wdenkc6097192002-11-03 00:24:07 +000021#include <asm/processor.h>
22#include <asm/io.h>
23#include <pci.h>
24
Bin Meng8f9052f2014-12-30 22:53:21 +080025DECLARE_GLOBAL_DATA_PTR;
26
wdenkf07771c2003-05-28 08:06:31 +000027#define PCI_HOSE_OP(rw, size, type) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020028int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
29 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000030 int offset, type value) \
31{ \
32 return hose->rw##_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000033}
34
35PCI_HOSE_OP(read, byte, u8 *)
36PCI_HOSE_OP(read, word, u16 *)
37PCI_HOSE_OP(read, dword, u32 *)
38PCI_HOSE_OP(write, byte, u8)
39PCI_HOSE_OP(write, word, u16)
40PCI_HOSE_OP(write, dword, u32)
41
wdenkf07771c2003-05-28 08:06:31 +000042#define PCI_OP(rw, size, type, error_code) \
43int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
44{ \
45 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
46 \
47 if (!hose) \
48 { \
49 error_code; \
50 return -1; \
51 } \
52 \
53 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000054}
55
56PCI_OP(read, byte, u8 *, *value = 0xff)
57PCI_OP(read, word, u16 *, *value = 0xffff)
58PCI_OP(read, dword, u32 *, *value = 0xffffffff)
59PCI_OP(write, byte, u8, )
60PCI_OP(write, word, u16, )
61PCI_OP(write, dword, u32, )
62
wdenkf07771c2003-05-28 08:06:31 +000063#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
64int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000066 int offset, type val) \
67{ \
68 u32 val32; \
69 \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090070 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
71 *val = -1; \
wdenkf07771c2003-05-28 08:06:31 +000072 return -1; \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090073 } \
wdenkf07771c2003-05-28 08:06:31 +000074 \
75 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
76 \
77 return 0; \
wdenkc6097192002-11-03 00:24:07 +000078}
79
wdenkf07771c2003-05-28 08:06:31 +000080#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
81int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
Wolfgang Denk53677ef2008-05-20 16:00:29 +020082 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000083 int offset, type val) \
84{ \
wdenk498b8db2004-04-18 22:26:17 +000085 u32 val32, mask, ldata, shift; \
wdenkf07771c2003-05-28 08:06:31 +000086 \
87 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88 return -1; \
89 \
wdenk498b8db2004-04-18 22:26:17 +000090 shift = ((offset & (int)off_mask) * 8); \
91 ldata = (((unsigned long)val) & val_mask) << shift; \
92 mask = val_mask << shift; \
wdenkf07771c2003-05-28 08:06:31 +000093 val32 = (val32 & ~mask) | ldata; \
94 \
95 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
96 return -1; \
97 \
98 return 0; \
wdenkc6097192002-11-03 00:24:07 +000099}
100
101PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
102PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
103PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
104PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
105
106/*
107 *
108 */
109
John Schmoller96d61602010-10-22 00:20:23 -0500110static struct pci_controller* hose_head;
wdenkc6097192002-11-03 00:24:07 +0000111
Bin Meng8f9052f2014-12-30 22:53:21 +0800112struct pci_controller *pci_get_hose_head(void)
113{
114 if (gd->hose)
115 return gd->hose;
116
117 return hose_head;
118}
119
wdenkc6097192002-11-03 00:24:07 +0000120void pci_register_hose(struct pci_controller* hose)
121{
122 struct pci_controller **phose = &hose_head;
123
124 while(*phose)
125 phose = &(*phose)->next;
126
127 hose->next = NULL;
128
129 *phose = hose;
130}
131
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000132struct pci_controller *pci_bus_to_hose(int bus)
wdenkc6097192002-11-03 00:24:07 +0000133{
134 struct pci_controller *hose;
135
Bin Meng8f9052f2014-12-30 22:53:21 +0800136 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
wdenkf07771c2003-05-28 08:06:31 +0000137 if (bus >= hose->first_busno && bus <= hose->last_busno)
wdenkc6097192002-11-03 00:24:07 +0000138 return hose;
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000139 }
wdenkc6097192002-11-03 00:24:07 +0000140
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200141 printf("pci_bus_to_hose() failed\n");
wdenkc6097192002-11-03 00:24:07 +0000142 return NULL;
143}
144
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600145struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
146{
147 struct pci_controller *hose;
148
Bin Meng8f9052f2014-12-30 22:53:21 +0800149 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600150 if (hose->cfg_addr == cfg_addr)
151 return hose;
152 }
153
154 return NULL;
155}
156
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300157int pci_last_busno(void)
158{
Bin Meng8f9052f2014-12-30 22:53:21 +0800159 struct pci_controller *hose = pci_get_hose_head();
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300160
161 if (!hose)
162 return -1;
163
164 while (hose->next)
165 hose = hose->next;
166
167 return hose->last_busno;
168}
169
wdenkc6097192002-11-03 00:24:07 +0000170pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
171{
172 struct pci_controller * hose;
wdenkc6097192002-11-03 00:24:07 +0000173 pci_dev_t bdf;
Simon Glassaab67242015-03-05 12:25:24 -0700174 int bus;
wdenkc6097192002-11-03 00:24:07 +0000175
Bin Meng8f9052f2014-12-30 22:53:21 +0800176 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
Simon Glassaab67242015-03-05 12:25:24 -0700177 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
Simon Glassaab67242015-03-05 12:25:24 -0700178 bdf = pci_hose_find_devices(hose, bus, ids, &index);
179 if (bdf != -1)
Simon Glass250e0392015-01-27 22:13:27 -0700180 return bdf;
Simon Glass250e0392015-01-27 22:13:27 -0700181 }
182 }
183
Simon Glassaab67242015-03-05 12:25:24 -0700184 return -1;
wdenkc6097192002-11-03 00:24:07 +0000185}
186
wdenkc6097192002-11-03 00:24:07 +0000187int pci_hose_config_device(struct pci_controller *hose,
188 pci_dev_t dev,
189 unsigned long io,
Kumar Gala30e76d52008-10-21 08:36:08 -0500190 pci_addr_t mem,
wdenkc6097192002-11-03 00:24:07 +0000191 unsigned long command)
192{
Kumar Galacf5787f2012-09-19 04:47:36 +0000193 u32 bar_response;
Andrew Sharpaf778c62012-08-01 12:27:16 +0000194 unsigned int old_command;
Kumar Gala30e76d52008-10-21 08:36:08 -0500195 pci_addr_t bar_value;
196 pci_size_t bar_size;
wdenkc6097192002-11-03 00:24:07 +0000197 unsigned char pin;
198 int bar, found_mem64;
199
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000200 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
201 (u64)mem, command);
wdenkc6097192002-11-03 00:24:07 +0000202
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000203 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
wdenkc6097192002-11-03 00:24:07 +0000204
Wolfgang Denk252b4042010-03-09 14:27:25 +0100205 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000206 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
207 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
wdenkc6097192002-11-03 00:24:07 +0000208
209 if (!bar_response)
210 continue;
211
212 found_mem64 = 0;
213
214 /* Check the BAR type and set our address mask */
wdenkf07771c2003-05-28 08:06:31 +0000215 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
wdenkc6097192002-11-03 00:24:07 +0000216 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000217 /* round up region base address to a multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000218 io = ((io - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000219 bar_value = io;
220 /* compute new region base address */
221 io = io + bar_size;
222 } else {
223 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -0500224 PCI_BASE_ADDRESS_MEM_TYPE_64) {
225 u32 bar_response_upper;
226 u64 bar64;
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000227 pci_hose_write_config_dword(hose, dev, bar + 4,
228 0xffffffff);
229 pci_hose_read_config_dword(hose, dev, bar + 4,
230 &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +0000231
Kumar Gala30e76d52008-10-21 08:36:08 -0500232 bar64 = ((u64)bar_response_upper << 32) | bar_response;
233
234 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
235 found_mem64 = 1;
236 } else {
237 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
238 }
wdenkc6097192002-11-03 00:24:07 +0000239
wdenkf07771c2003-05-28 08:06:31 +0000240 /* round up region base address to multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000241 mem = ((mem - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000242 bar_value = mem;
243 /* compute new region base address */
244 mem = mem + bar_size;
wdenkc6097192002-11-03 00:24:07 +0000245 }
246
247 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500248 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000249
wdenkf07771c2003-05-28 08:06:31 +0000250 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000251 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500252#ifdef CONFIG_SYS_PCI_64BIT
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000253 pci_hose_write_config_dword(hose, dev, bar,
254 (u32)(bar_value >> 32));
Kumar Gala30e76d52008-10-21 08:36:08 -0500255#else
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000256 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500257#endif
wdenkc6097192002-11-03 00:24:07 +0000258 }
259 }
260
261 /* Configure Cache Line Size Register */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000262 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
wdenkc6097192002-11-03 00:24:07 +0000263
264 /* Configure Latency Timer */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000265 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
wdenkc6097192002-11-03 00:24:07 +0000266
267 /* Disable interrupt line, if device says it wants to use interrupts */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000268 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
wdenkf07771c2003-05-28 08:06:31 +0000269 if (pin != 0) {
Simon Glass5f48d792015-07-27 15:47:17 -0600270 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
271 PCI_INTERRUPT_LINE_DISABLE);
wdenkc6097192002-11-03 00:24:07 +0000272 }
273
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000274 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
275 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
wdenkf07771c2003-05-28 08:06:31 +0000276 (old_command & 0xffff0000) | command);
wdenkc6097192002-11-03 00:24:07 +0000277
278 return 0;
279}
280
281/*
282 *
283 */
284
285struct pci_config_table *pci_find_config(struct pci_controller *hose,
286 unsigned short class,
287 unsigned int vendor,
288 unsigned int device,
289 unsigned int bus,
290 unsigned int dev,
291 unsigned int func)
292{
293 struct pci_config_table *table;
294
wdenkf07771c2003-05-28 08:06:31 +0000295 for (table = hose->config_table; table && table->vendor; table++) {
wdenkc6097192002-11-03 00:24:07 +0000296 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
297 (table->device == PCI_ANY_ID || table->device == device) &&
298 (table->class == PCI_ANY_ID || table->class == class) &&
299 (table->bus == PCI_ANY_ID || table->bus == bus) &&
300 (table->dev == PCI_ANY_ID || table->dev == dev) &&
wdenkf07771c2003-05-28 08:06:31 +0000301 (table->func == PCI_ANY_ID || table->func == func)) {
wdenkc6097192002-11-03 00:24:07 +0000302 return table;
303 }
304 }
305
306 return NULL;
307}
308
309void pci_cfgfunc_config_device(struct pci_controller *hose,
310 pci_dev_t dev,
311 struct pci_config_table *entry)
312{
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000313 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
314 entry->priv[2]);
wdenkc6097192002-11-03 00:24:07 +0000315}
316
317void pci_cfgfunc_do_nothing(struct pci_controller *hose,
318 pci_dev_t dev, struct pci_config_table *entry)
319{
320}
321
322/*
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000323 * HJF: Changed this to return int. I think this is required
wdenkc7de8292002-11-19 11:04:11 +0000324 * to get the correct result when scanning bridges
325 */
326extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000327
Stefan Roesedc1da422008-07-08 12:01:47 +0200328#ifdef CONFIG_PCI_SCAN_SHOW
Jeroen Hofstee7b19fd62014-10-08 22:57:27 +0200329__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
Stefan Roesedc1da422008-07-08 12:01:47 +0200330{
331 if (dev == PCI_BDF(hose->first_busno, 0, 0))
332 return 0;
333
334 return 1;
335}
Stefan Roesedc1da422008-07-08 12:01:47 +0200336#endif /* CONFIG_PCI_SCAN_SHOW */
337
wdenkc6097192002-11-03 00:24:07 +0000338int pci_hose_scan_bus(struct pci_controller *hose, int bus)
339{
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000340 unsigned int sub_bus, found_multi = 0;
wdenkc6097192002-11-03 00:24:07 +0000341 unsigned short vendor, device, class;
342 unsigned char header_type;
Andrew Sharp03992ac2012-08-29 14:16:30 +0000343#ifndef CONFIG_PCI_PNP
wdenkc6097192002-11-03 00:24:07 +0000344 struct pci_config_table *cfg;
Andrew Sharp03992ac2012-08-29 14:16:30 +0000345#endif
wdenkc6097192002-11-03 00:24:07 +0000346 pci_dev_t dev;
Peter Tyser009884a2010-10-29 17:59:29 -0500347#ifdef CONFIG_PCI_SCAN_SHOW
348 static int indent = 0;
349#endif
wdenkc6097192002-11-03 00:24:07 +0000350
351 sub_bus = bus;
352
353 for (dev = PCI_BDF(bus,0,0);
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000354 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
355 PCI_MAX_PCI_FUNCTIONS - 1);
356 dev += PCI_BDF(0, 0, 1)) {
Stefan Roesedc1da422008-07-08 12:01:47 +0200357
358 if (pci_skip_dev(hose, dev))
359 continue;
wdenkc6097192002-11-03 00:24:07 +0000360
361 if (PCI_FUNC(dev) && !found_multi)
362 continue;
363
364 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
365
366 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
367
Peter Tyser983eb9d2010-10-29 17:59:27 -0500368 if (vendor == 0xffff || vendor == 0x0000)
369 continue;
wdenkc6097192002-11-03 00:24:07 +0000370
Peter Tyser983eb9d2010-10-29 17:59:27 -0500371 if (!PCI_FUNC(dev))
372 found_multi = header_type & 0x80;
wdenkc6097192002-11-03 00:24:07 +0000373
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000374 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
375 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
wdenkc6097192002-11-03 00:24:07 +0000376
Peter Tyser983eb9d2010-10-29 17:59:27 -0500377 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
378 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
wdenkc6097192002-11-03 00:24:07 +0000379
Tim Harvey09918662014-08-07 22:49:56 -0700380#ifdef CONFIG_PCI_FIXUP_DEV
381 board_pci_fixup_dev(hose, dev, vendor, device, class);
382#endif
383
Peter Tysera38d2162010-10-29 17:59:28 -0500384#ifdef CONFIG_PCI_SCAN_SHOW
Peter Tyser009884a2010-10-29 17:59:29 -0500385 indent++;
386
387 /* Print leading space, including bus indentation */
388 printf("%*c", indent + 1, ' ');
389
Peter Tysera38d2162010-10-29 17:59:28 -0500390 if (pci_print_dev(hose, dev)) {
Peter Tyser009884a2010-10-29 17:59:29 -0500391 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
392 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
Peter Tysera38d2162010-10-29 17:59:28 -0500393 vendor, device, pci_class_str(class >> 8));
394 }
395#endif
396
Andrew Sharp03992ac2012-08-29 14:16:30 +0000397#ifdef CONFIG_PCI_PNP
Masahiro Yamadab4141192014-11-07 03:03:31 +0900398 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
399 sub_bus);
Andrew Sharp03992ac2012-08-29 14:16:30 +0000400#else
Peter Tyser983eb9d2010-10-29 17:59:27 -0500401 cfg = pci_find_config(hose, class, vendor, device,
402 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
403 if (cfg) {
404 cfg->config_device(hose, dev, cfg);
Masahiro Yamadab4141192014-11-07 03:03:31 +0900405 sub_bus = max(sub_bus,
406 (unsigned int)hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000407 }
Andrew Sharp03992ac2012-08-29 14:16:30 +0000408#endif
Peter Tysera38d2162010-10-29 17:59:28 -0500409
Peter Tyser009884a2010-10-29 17:59:29 -0500410#ifdef CONFIG_PCI_SCAN_SHOW
411 indent--;
412#endif
413
Peter Tyser983eb9d2010-10-29 17:59:27 -0500414 if (hose->fixup_irq)
415 hose->fixup_irq(hose, dev);
wdenkc6097192002-11-03 00:24:07 +0000416 }
417
418 return sub_bus;
419}
420
421int pci_hose_scan(struct pci_controller *hose)
422{
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000423#if defined(CONFIG_PCI_BOOTDELAY)
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000424 char *s;
425 int i;
426
Bin Meng8f9052f2014-12-30 22:53:21 +0800427 if (!gd->pcidelay_done) {
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000428 /* wait "pcidelay" ms (if defined)... */
Simon Glass00caae62017-08-03 12:22:12 -0600429 s = env_get("pcidelay");
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000430 if (s) {
431 int val = simple_strtoul(s, NULL, 10);
432 for (i = 0; i < val; i++)
433 udelay(1000);
434 }
Bin Meng8f9052f2014-12-30 22:53:21 +0800435 gd->pcidelay_done = 1;
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000436 }
437#endif /* CONFIG_PCI_BOOTDELAY */
438
Tim Harvey0373a7e2015-05-08 15:16:07 -0700439#ifdef CONFIG_PCI_SCAN_SHOW
440 puts("PCI:\n");
441#endif
442
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000443 /*
444 * Start scan at current_busno.
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500445 * PCIe will start scan at first_busno+1.
446 */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000447 /* For legacy support, ensure current >= first */
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500448 if (hose->first_busno > hose->current_busno)
449 hose->current_busno = hose->first_busno;
wdenkc6097192002-11-03 00:24:07 +0000450#ifdef CONFIG_PCI_PNP
451 pciauto_config_init(hose);
452#endif
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500453 return pci_hose_scan_bus(hose, hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000454}
455
stroesead10dd92003-02-14 11:21:23 +0000456void pci_init(void)
457{
John Schmoller96d61602010-10-22 00:20:23 -0500458 hose_head = NULL;
459
Tim Harveyec21aee2016-06-17 06:20:25 -0700460 /* allow env to disable pci init/enum */
Simon Glass00caae62017-08-03 12:22:12 -0600461 if (env_get("pcidisable") != NULL)
Tim Harveyec21aee2016-06-17 06:20:25 -0700462 return;
463
stroesead10dd92003-02-14 11:21:23 +0000464 /* now call board specific pci_init()... */
465 pci_init_board();
466}
Zhao Qiang287df012013-10-12 13:46:33 +0800467
468/* Returns the address of the requested capability structure within the
469 * device's PCI configuration space or 0 in case the device does not
470 * support it.
471 * */
472int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
473 int cap)
474{
475 int pos;
476 u8 hdr_type;
477
478 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
479
480 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
481
482 if (pos)
483 pos = pci_find_cap(hose, dev, pos, cap);
484
485 return pos;
486}
487
488/* Find the header pointer to the Capabilities*/
489int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
490 u8 hdr_type)
491{
492 u16 status;
493
494 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
495
496 if (!(status & PCI_STATUS_CAP_LIST))
497 return 0;
498
499 switch (hdr_type) {
500 case PCI_HEADER_TYPE_NORMAL:
501 case PCI_HEADER_TYPE_BRIDGE:
502 return PCI_CAPABILITY_LIST;
503 case PCI_HEADER_TYPE_CARDBUS:
504 return PCI_CB_CAPABILITY_LIST;
505 default:
506 return 0;
507 }
508}
509
510int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
511{
512 int ttl = PCI_FIND_CAP_TTL;
513 u8 id;
514 u8 next_pos;
515
516 while (ttl--) {
517 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
518 if (next_pos < CAP_START_POS)
519 break;
520 next_pos &= ~3;
521 pos = (int) next_pos;
522 pci_hose_read_config_byte(hose, dev,
523 pos + PCI_CAP_LIST_ID, &id);
524 if (id == 0xff)
525 break;
526 if (id == cap)
527 return pos;
528 pos += PCI_CAP_LIST_NEXT;
529 }
530 return 0;
531}
Minghuan Lianed5b5802015-07-10 11:35:08 +0800532
533/**
534 * pci_find_next_ext_capability - Find an extended capability
535 *
536 * Returns the address of the next matching extended capability structure
537 * within the device's PCI configuration space or 0 if the device does
538 * not support it. Some capabilities can occur several times, e.g., the
539 * vendor-specific capability, and this provides a way to find them all.
540 */
541int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
542 int start, int cap)
543{
544 u32 header;
545 int ttl, pos = PCI_CFG_SPACE_SIZE;
546
547 /* minimum 8 bytes per capability */
548 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549
550 if (start)
551 pos = start;
552
553 pci_hose_read_config_dword(hose, dev, pos, &header);
554 if (header == 0xffffffff || header == 0)
555 return 0;
556
557 while (ttl-- > 0) {
558 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
559 return pos;
560
561 pos = PCI_EXT_CAP_NEXT(header);
562 if (pos < PCI_CFG_SPACE_SIZE)
563 break;
564
565 pci_hose_read_config_dword(hose, dev, pos, &header);
566 if (header == 0xffffffff || header == 0)
567 break;
568 }
569
570 return 0;
571}
572
573/**
574 * pci_hose_find_ext_capability - Find an extended capability
575 *
576 * Returns the address of the requested extended capability structure
577 * within the device's PCI configuration space or 0 if the device does
578 * not support it.
579 */
580int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
581 int cap)
582{
583 return pci_find_next_ext_capability(hose, dev, 0, cap);
584}