blob: 0f29cd122c7316571469df689417cb571148cc2a [file] [log] [blame]
wdenke0648062002-08-20 00:12:21 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
37#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFE000000
40
wdenke0648062002-08-20 00:12:21 +000041#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 9600
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
55#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
56
57#undef CONFIG_BOOTARGS
58#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020059 "bootp; " \
60 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke0648062002-08-20 00:12:21 +000062 "bootm"
63
64#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke0648062002-08-20 00:12:21 +000066
67#undef CONFIG_WATCHDOG /* watchdog disabled */
68
Jon Loeliger48d5d102007-07-04 22:32:25 -050069
70/*
71 * Command line configuration.
72 */
73#include <config_cmd_default.h>
74
wdenke0648062002-08-20 00:12:21 +000075
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050076/*
77 * BOOTP options
78 */
79#define CONFIG_BOOTP_SUBNETMASK
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82#define CONFIG_BOOTP_BOOTPATH
83
wdenke0648062002-08-20 00:12:21 +000084
wdenke0648062002-08-20 00:12:21 +000085/*
86 * Miscellaneous configurable options
87 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_LONGHELP /* undef to save memory */
89#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -050090#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke0648062002-08-20 00:12:21 +000092#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke0648062002-08-20 00:12:21 +000094#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke0648062002-08-20 00:12:21 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
100#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenke0648062002-08-20 00:12:21 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenke0648062002-08-20 00:12:21 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenke0648062002-08-20 00:12:21 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke0648062002-08-20 00:12:21 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
wdenke0648062002-08-20 00:12:21 +0000109/*
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
113 */
114/*-----------------------------------------------------------------------
115 * Internal Memory Mapped Register
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
wdenke0648062002-08-20 00:12:21 +0000118
119/*-----------------------------------------------------------------------
120 * Definitions for initial stack pointer and data area (in DPRAM)
121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200123#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200124#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke0648062002-08-20 00:12:21 +0000126
127/*-----------------------------------------------------------------------
128 * Start addresses for the final memory configuration
129 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke0648062002-08-20 00:12:21 +0000131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_SDRAM_BASE 0x00000000
133#define CONFIG_SYS_FLASH_BASE 0xFE000000
wdenke0648062002-08-20 00:12:21 +0000134#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenke0648062002-08-20 00:12:21 +0000136#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke0648062002-08-20 00:12:21 +0000138#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
140#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke0648062002-08-20 00:12:21 +0000141
142/*
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization.
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke0648062002-08-20 00:12:21 +0000148/*-----------------------------------------------------------------------
149 * FLASH organization
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
152#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
wdenke0648062002-08-20 00:12:21 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
155#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke0648062002-08-20 00:12:21 +0000156
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200157#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200158#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
159#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
wdenke0648062002-08-20 00:12:21 +0000160/*-----------------------------------------------------------------------
161 * Cache Configuration
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500164#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke0648062002-08-20 00:12:21 +0000166#endif
167
168/*-----------------------------------------------------------------------
169 * SYPCR - System Protection Control 11-9
170 * SYPCR can only be written once after reset!
171 *-----------------------------------------------------------------------
172 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
173 * +0x0004
174 */
175#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke0648062002-08-20 00:12:21 +0000177 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
178#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke0648062002-08-20 00:12:21 +0000180#endif
181
182/*-----------------------------------------------------------------------
183 * SIUMCR - SIU Module Configuration 11-6
184 *-----------------------------------------------------------------------
185 * +0x0000 => 0x000000C0
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SIUMCR 0
wdenke0648062002-08-20 00:12:21 +0000188
189/*-----------------------------------------------------------------------
190 * TBSCR - Time Base Status and Control 11-26
191 *-----------------------------------------------------------------------
192 * Clear Reference Interrupt Status, Timebase freezing enabled
193 * +0x0200 => 0x00C2
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke0648062002-08-20 00:12:21 +0000196
197/*-----------------------------------------------------------------------
198 * PISCR - Periodic Interrupt Status and Control 11-31
199 *-----------------------------------------------------------------------
200 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
201 * +0x0240 => 0x0082
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenke0648062002-08-20 00:12:21 +0000204
205/*-----------------------------------------------------------------------
206 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
207 *-----------------------------------------------------------------------
208 * Reset PLL lock status sticky bit, timer expired status bit and timer
209 * interrupt status bit, set PLL multiplication factor !
210 */
211/* +0x0286 => 0x00B0D0C0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_PLPRCR \
wdenke0648062002-08-20 00:12:21 +0000213 ( (11 << PLPRCR_MF_SHIFT) | \
214 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
215 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
216 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
217 )
218
219/*-----------------------------------------------------------------------
220 * SCCR - System Clock and reset Control Register 15-27
221 *-----------------------------------------------------------------------
222 * Set clock output, timebase and RTC source and divider,
223 * power management and some other internal clocks
224 */
225#define SCCR_MASK SCCR_EBDF11
226/* +0x0282 => 0x03800000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
wdenke0648062002-08-20 00:12:21 +0000228 SCCR_RTDIV | SCCR_RTSEL | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200229 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
wdenke0648062002-08-20 00:12:21 +0000230 SCCR_EBDF00 | SCCR_DFSYNC00 | \
231 SCCR_DFBRG00 | SCCR_DFNL000 | \
232 SCCR_DFNH000)
233
234/*-----------------------------------------------------------------------
235 * RTCSC - Real-Time Clock Status and Control Register 11-27
236 *-----------------------------------------------------------------------
237 */
238/* +0x0220 => 0x00C3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke0648062002-08-20 00:12:21 +0000240
241
242/*-----------------------------------------------------------------------
243 * RCCR - RISC Controller Configuration Register 19-4
244 *-----------------------------------------------------------------------
245 */
246/* +0x09C4 => TIMEP=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_RCCR 0x0100
wdenke0648062002-08-20 00:12:21 +0000248
249/*-----------------------------------------------------------------------
250 * RMDS - RISC Microcode Development Support Control Register
251 *-----------------------------------------------------------------------
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_RMDS 0
wdenke0648062002-08-20 00:12:21 +0000254
255/*-----------------------------------------------------------------------
256 *
257 *-----------------------------------------------------------------------
258 *
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_DER 0
wdenke0648062002-08-20 00:12:21 +0000261
262/*
263 * Init Memory Controller:
264 *
265 * BR0 and OR0 (FLASH)
266 */
267
268#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
269
270/* used to re-map FLASH
271 * restrict access enough to keep SRAM working (if any)
272 * but not too much to meddle with FLASH accesses
273 */
274/* allow for max 4 MB of Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
276#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
wdenke0648062002-08-20 00:12:21 +0000277
278/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
wdenke0648062002-08-20 00:12:21 +0000280 OR_SCY_5_CLK | OR_TRLX)
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
283#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenke0648062002-08-20 00:12:21 +0000284/* 8 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenke0648062002-08-20 00:12:21 +0000286
287/*
288 * BR1/OR1 - SDRAM
289 *
290 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
291 */
292#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
293#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
294#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
295
296#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
299#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke0648062002-08-20 00:12:21 +0000300
301/*
302 * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
303 */
304#define HPRO2_BASE 0xE0000000
305#define HPRO2_OR_AM 0xFFFF8000
306#define HPRO2_TIMING 0x00000934
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
309#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenke0648062002-08-20 00:12:21 +0000310
311/*
312 * BR3/OR3: not used
313 * BR4/OR4: not used
314 * BR5/OR5: not used
315 * BR6/OR6: not used
316 * BR7/OR7: not used
317 */
318
319/*
320 * MAMR settings for SDRAM
321 */
322
323/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenke0648062002-08-20 00:12:21 +0000325
326/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke0648062002-08-20 00:12:21 +0000328 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
329 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
330/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke0648062002-08-20 00:12:21 +0000332 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
333 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenke0648062002-08-20 00:12:21 +0000334#endif /* __CONFIG_H */