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Peter Barada86887f82011-12-19 19:54:51 +00001/*
2 * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
3 * Peter Barada <peter.barada@logicpd.com>
4 *
5 * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
6 * reference boards.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_OMAP /* in a TI OMAP core */
34#define CONFIG_OMAP34XX /* which is a 34XX */
35#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
Marek Vasut308252a2012-07-21 05:02:23 +000036#define CONFIG_OMAP_GPIO
Peter Barada86887f82011-12-19 19:54:51 +000037
Peter Barada86887f82011-12-19 19:54:51 +000038#define CONFIG_SYS_TEXT_BASE 0x80400000
39
40#define CONFIG_SDRC /* The chip has SDRC controller */
41
42#include <asm/arch/cpu.h> /* get chip and board defs */
43#include <asm/arch/omap3.h>
44
45/*
46 * Display CPU and Board information
47 */
48#define CONFIG_DISPLAY_CPUINFO
49#define CONFIG_DISPLAY_BOARDINFO
50
51/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
55#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
56
57#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
58#define CONFIG_SETUP_MEMORY_TAGS
59#define CONFIG_INITRD_TAG
60#define CONFIG_REVISION_TAG
61
62#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
63#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
64
65/*
66 * Size of malloc() pool
67 */
68#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
69 /* Sector */
70#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
71
72/*
73 * Hardware drivers
74 */
75
76/*
77 * NS16550 Configuration
78 */
79#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85
86/*
87 * select serial console configuration
88 */
89#define CONFIG_CONS_INDEX 1
90#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
91#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
92
93/* allow to overwrite serial and ethaddr */
94#define CONFIG_ENV_OVERWRITE
95#define CONFIG_BAUDRATE 115200
96#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 115200}
98#define CONFIG_GENERIC_MMC
99#define CONFIG_MMC
100#define CONFIG_OMAP_HSMMC
101#define CONFIG_DOS_PARTITION
102
103/* commands to include */
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_CACHE
107#define CONFIG_CMD_EXT2 /* EXT2 Support */
108#define CONFIG_CMD_FAT /* FAT support */
109#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
110#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
111#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
112#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
113#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
114 "1920k(u-boot),128k(u-boot-env),"\
115 "4m(kernel),-(fs)"
116
117#define CONFIG_CMD_I2C /* I2C serial bus support */
118#define CONFIG_CMD_MMC /* MMC support */
119#define CONFIG_CMD_NAND /* NAND support */
120#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
121#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
122#define CONFIG_CMD_PING
123#define CONFIG_CMD_DHCP
Marek Vasut02b233e2012-03-31 07:47:18 +0000124#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
Peter Barada86887f82011-12-19 19:54:51 +0000125
126#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
127#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
128#undef CONFIG_CMD_IMI /* iminfo */
129#undef CONFIG_CMD_IMLS /* List all found images */
130
131#define CONFIG_SYS_NO_FLASH
132
133/*
134 * I2C
135 */
136#define CONFIG_HARD_I2C
137#define CONFIG_DRIVER_OMAP34XX_I2C
138
139#define CONFIG_SYS_I2C_SPEED 100000
140#define CONFIG_SYS_I2C_SLAVE 1
Peter Barada86887f82011-12-19 19:54:51 +0000141#define CONFIG_I2C_MULTI_BUS
142
143/*
144 * TWL4030
145 */
146#define CONFIG_TWL4030_POWER
147
148/*
149 * Board NAND Info.
150 */
151#define CONFIG_SYS_NAND_QUIET_TEST
152#define CONFIG_NAND_OMAP_GPMC
153#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
154 /* to access nand */
155#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
156 /* to access nand at */
157 /* CS0 */
158
159#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
160 /* NAND devices */
161#define CONFIG_JFFS2_NAND
162/* nand device jffs2 lives on */
163#define CONFIG_JFFS2_DEV "nand0"
164/* start of jffs2 partition */
165#define CONFIG_JFFS2_PART_OFFSET 0x680000
166#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
167 /* partition */
168
169/* Environment information */
170#define CONFIG_BOOTDELAY 2
171
172/*
173 * PREBOOT assumes the 4.3" display is attached. User can interrupt
174 * and modify display variable to suit their needs.
175 */
176#define CONFIG_PREBOOT \
177 "echo ======================NOTICE============================;"\
178 "echo \"The u-boot environment is not set.\";" \
179 "echo \"If using a display a valid display varible for your panel\";" \
180 "echo \"needs to be set.\";" \
181 "echo \"Valid display options are:\";" \
182 "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
183 "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
184 "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
185 "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
186 "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
187 "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
188 "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
189 "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
190 "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
191 "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
192 "setenv display 15;" \
193 "setenv preboot;" \
194 "saveenv;"
195
196
197#define CONFIG_EXTRA_ENV_SETTINGS \
198 "loadaddr=0x81000000\0" \
199 "bootfile=uImage\0" \
200 "mtdids=" MTDIDS_DEFAULT "\0" \
201 "mtdparts=" MTDPARTS_DEFAULT "\0" \
202 "mmcdev=0\0" \
Andrew Bradford66968112012-10-01 05:06:52 +0000203 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
Peter Barada86887f82011-12-19 19:54:51 +0000204 "if run loadbootscript; then " \
205 "run bootscript; " \
206 "else " \
207 "run defaultboot;" \
208 "fi; " \
209 "else run defaultboot; fi\0" \
210 "defaultboot=run mmcramboot\0" \
211 "consoledevice=ttyO0\0" \
212 "display=15\0" \
213 "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
214 "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
215 "rotation=0\0" \
216 "vrfb_arg=if itest ${rotation} -ne 0; then " \
217 "setenv bootargs ${bootargs} omapfb.vrfb=y " \
218 "omapfb.rotate=${rotation}; " \
219 "fi\0" \
220 "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
221 "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
222 "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
223 "${otherbootargs};" \
224 "run addmtdparts; " \
225 "run vrfb_arg\0" \
226 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
227 "bootscript=echo 'Running bootscript from mmc ...'; " \
228 "source ${loadaddr}\0" \
229 "loaduimage=mmc rescan ${mmcdev}; " \
230 "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
231 "ramdisksize=64000\0" \
232 "ramdiskaddr=0x82000000\0" \
233 "ramdiskimage=rootfs.ext2.gz.uboot\0" \
234 "ramargs=run setconsole; setenv bootargs console=${console} " \
235 "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
236 "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
237 "run ramargs; " \
238 "run common_bootargs; " \
239 "run dump_bootargs; " \
240 "run loaduimage; " \
241 "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
242 "bootm ${loadaddr} ${ramdiskaddr}\0" \
243 "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
244 "run ramargs; " \
245 "run common_bootargs; " \
246 "run dump_bootargs; " \
247 "tftpboot ${loadaddr} ${bootfile}; "\
248 "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
249 "bootm ${loadaddr} ${ramdiskaddr}\0"
250
251#define CONFIG_BOOTCOMMAND \
252 "run autoboot"
253
254#define CONFIG_AUTO_COMPLETE
255/*
256 * Miscellaneous configurable options
257 */
258#define CONFIG_SYS_LONGHELP /* undef to save memory */
259#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Peter Barada86887f82011-12-19 19:54:51 +0000260#define CONFIG_SYS_PROMPT "OMAP Logic # "
261#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
262/* Print Buffer Size */
263#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
264 sizeof(CONFIG_SYS_PROMPT) + 16)
265#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
266/* Boot Argument Buffer Size */
267#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
268/* memtest works on */
269#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
270#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
271 0x01F00000) /* 31MB */
272
273#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
274 /* address */
275
276/*
277 * OMAP3 has 12 GP timers, they can be driven by the system clock
278 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
279 * This rate is divided by a local divisor.
280 */
281#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
282#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
283#define CONFIG_SYS_HZ 1000
284
285/*
Peter Barada86887f82011-12-19 19:54:51 +0000286 * Physical Memory Map
287 */
288#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
289#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
290#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
291
292/*
293 * FLASH and environment organization
294 */
295
296/* **** PISMO SUPPORT *** */
297
298/* Configure the PISMO */
299#define PISMO1_NAND_SIZE GPMC_SIZE_128M
300
301#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
302
303#if defined(CONFIG_CMD_NAND)
304#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
305#elif defined(CONFIG_CMD_ONENAND)
306#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
307#endif
308
309/* Monitor at start of flash */
310#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
311
312#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
313
314#if defined(CONFIG_CMD_NAND)
315#define CONFIG_NAND_OMAP_GPMC
316#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
317#define CONFIG_ENV_IS_IN_NAND
318#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
319#endif
320
321#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
322#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
323
324#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
325#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
326#define CONFIG_SYS_INIT_RAM_SIZE 0x800
327#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
328 CONFIG_SYS_INIT_RAM_SIZE - \
329 GENERATED_GBL_DATA_SIZE)
330
331/*
332 * SMSC922x Ethernet
333 */
334#if defined(CONFIG_CMD_NET)
335
336#define CONFIG_SMC911X
337#define CONFIG_SMC911X_16_BIT
338#define CONFIG_SMC911X_BASE 0x08000000
339
340#endif /* (CONFIG_CMD_NET) */
341
342/*
343 * BOOTP fields
344 */
345
346#define CONFIG_BOOTP_SUBNETMASK 0x00000001
347#define CONFIG_BOOTP_GATEWAY 0x00000002
348#define CONFIG_BOOTP_HOSTNAME 0x00000004
349#define CONFIG_BOOTP_BOOTPATH 0x00000010
350
351#endif /* __CONFIG_H */