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wdenk9e3f8cd2002-09-15 14:08:13 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk9e3f8cd2002-09-15 14:08:13 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#include <mpc8xx_irq.h>
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MPC860 1
38#define CONFIG_MPC860T 1
39#define CONFIG_ICU862 1
40#define CONFIG_MPC862 1
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
47
48#ifdef CONFIG_100MHz
49#define MPC8XX_FACT 24 /* Multiply by 24 */
50#define MPC8XX_XIN 4165000 /* 4.165 MHz in */
51#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
52 /* define if cant' use get_gclk_freq */
53#else
54#if 1 /* for 50MHz version of processor */
55#define MPC8XX_FACT 12 /* Multiply by 12 */
56#define MPC8XX_XIN 4000000 /* 4 MHz in */
57#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
58#else /* for 80MHz version of processor */
59#define MPC8XX_FACT 20 /* Multiply by 20 */
60#define MPC8XX_XIN 4000000 /* 4 MHz in */
61#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
62#endif
63#endif
64
wdenk9e3f8cd2002-09-15 14:08:13 +000065#if 0
66#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
67#else
68#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
69#endif
70
71#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
72
73#undef CONFIG_BOOTARGS
74#define CONFIG_BOOTCOMMAND \
75 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
77 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk9e3f8cd2002-09-15 14:08:13 +000078 "bootm"
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
Jon Loeliger7be044e2007-07-09 21:24:19 -050084/*
85 * BOOTP options
86 */
87#define CONFIG_BOOTP_SUBNETMASK
88#define CONFIG_BOOTP_GATEWAY
89#define CONFIG_BOOTP_HOSTNAME
90#define CONFIG_BOOTP_BOOTPATH
91#define CONFIG_BOOTP_BOOTFILESIZE
92
wdenk9e3f8cd2002-09-15 14:08:13 +000093
94#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
95#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
Marian Balakowicz63ff0042005-10-28 22:30:33 +020096#define CONFIG_MII 1
wdenk9e3f8cd2002-09-15 14:08:13 +000097#if 1
98#define CFG_DISCOVER_PHY 1
99#else
100#undef CFG_DISCOVER_PHY
101#endif
102
103#define CONFIG_MAC_PARTITION
104#define CONFIG_DOS_PARTITION
105
106/* enable I2C and select the hardware/software driver */
107#undef CONFIG_HARD_I2C /* I2C with hardware support */
108#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109# define CFG_I2C_SPEED 50000
110# define CFG_I2C_SLAVE 0xFE
111# define CFG_I2C_EEPROM_ADDR 0x50
112# define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
113/*
114 * Software (bit-bang) I2C driver configuration
115 */
116#define PB_SCL 0x00000020 /* PB 26 */
117#define PB_SDA 0x00000010 /* PB 27 */
118
119#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
120#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
121#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
122#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
123#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
124 else immr->im_cpm.cp_pbdat &= ~PB_SDA
125#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
126 else immr->im_cpm.cp_pbdat &= ~PB_SCL
127#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
128
129#define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
130#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
131
132#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
133
wdenk9e3f8cd2002-09-15 14:08:13 +0000134
Jon Loeliger348f2582007-07-08 13:46:18 -0500135/*
136 * Command line configuration.
137 */
138#include <config_cmd_default.h>
139
140#define CONFIG_CMD_ASKENV
141#define CONFIG_CMD_DATE
142#define CONFIG_CMD_DHCP
143#define CONFIG_CMD_EEPROM
144#define CONFIG_CMD_I2C
145#define CONFIG_CMD_IDE
146#define CONFIG_CMD_NFS
147#define CONFIG_CMD_SNTP
148
wdenk9e3f8cd2002-09-15 14:08:13 +0000149
150/*
151 * Miscellaneous configurable options
152 */
153#define CFG_LONGHELP /* undef to save memory */
154#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500155#if defined(CONFIG_CMD_KGDB)
wdenk9e3f8cd2002-09-15 14:08:13 +0000156#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
157#else
158#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
159#endif
160#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
161#define CFG_MAXARGS 16 /* max number of command args */
162#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
163
164#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
165#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
166
167#define CFG_LOAD_ADDR 0x00100000
168
169#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
170
171#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
172
173/*
174 * Low Level Configuration Settings
175 * (address mappings, register initial values, etc.)
176 * You should know what you are doing if you make changes here.
177 */
178/*-----------------------------------------------------------------------
179 * Internal Memory Mapped Register
180 */
181#define CFG_IMMR 0xF0000000
182#define CFG_IMMR_SIZE ((uint)(64 * 1024))
183
184/*-----------------------------------------------------------------------
185 * Definitions for initial stack pointer and data area (in DPRAM)
186 */
187#define CFG_INIT_RAM_ADDR CFG_IMMR
188#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
189#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
190#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
191#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
192
193/*-----------------------------------------------------------------------
194 * Start addresses for the final memory configuration
195 * (Set up by the startup code)
196 * Please note that CFG_SDRAM_BASE _must_ start at 0
197 */
198#define CFG_SDRAM_BASE 0x00000000
199#define CFG_FLASH_BASE 0x40000000
200#define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
201
202#define CFG_RESET_ADDRESS 0xFFF00100
203
204#if 0
205#if defined(DEBUG)
206#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
207#else
208#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
209#endif
210#else
wdenkd94f92c2003-08-28 09:41:22 +0000211#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk9e3f8cd2002-09-15 14:08:13 +0000212#endif
213#define CFG_MONITOR_BASE TEXT_BASE
214#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
220 */
221#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222/*-----------------------------------------------------------------------
223 * FLASH organization
224 */
225#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
226#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
227
228#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
229#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
230
231
232#define CFG_ENV_IS_IN_FLASH 1
233#define CFG_ENV_OFFSET 0x00F40000
234
235#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
236#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200237#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk9e3f8cd2002-09-15 14:08:13 +0000238
239/*-----------------------------------------------------------------------
240 * Cache Configuration
241 */
242#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500243#if defined(CONFIG_CMD_KGDB)
wdenk9e3f8cd2002-09-15 14:08:13 +0000244#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
245#endif
246
247/*-----------------------------------------------------------------------
248 * SYPCR - System Protection Control 11-9
249 * SYPCR can only be written once after reset!
250 *-----------------------------------------------------------------------
251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 */
253#if defined(CONFIG_WATCHDOG)
254#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256#else
257#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
258#endif
259
260/*-----------------------------------------------------------------------
261 * SIUMCR - SIU Module Configuration 11-6
262 *-----------------------------------------------------------------------
263 * PCMCIA config., multi-function pin tri-state
264 */
265#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
266
267/*-----------------------------------------------------------------------
268 * TBSCR - Time Base Status and Control 11-26
269 *-----------------------------------------------------------------------
270 * Clear Reference Interrupt Status, Timebase freezing enabled
271 */
272#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
273
274/*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 11-31
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 */
279#define CFG_PISCR (PISCR_PS | PISCR_PITF)
280
281/*-----------------------------------------------------------------------
282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
283 *-----------------------------------------------------------------------
284 * set the PLL, the low-power modes and the reset control (15-29)
285 */
286#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
287 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
288
289/*-----------------------------------------------------------------------
290 * SCCR - System Clock and reset Control Register 15-27
291 *-----------------------------------------------------------------------
292 * Set clock output, timebase and RTC source and divider,
293 * power management and some other internal clocks
294 */
295#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
296#define SCCR_MASK 0
297#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
298 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
299 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
300#else /* up to 50 MHz we use a 1:1 clock */
301#define SCCR_MASK SCCR_EBDF11
302#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
303 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
304 SCCR_DFLCD000 |SCCR_DFALCD00 )
305#endif /* CONFIG_100MHz */
306
307/*-----------------------------------------------------------------------
308 * RCCR - RISC Controller Configuration Register 19-4
309 *-----------------------------------------------------------------------
310 */
311/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
312#define CFG_RCCR 0x0020
313
314/*-----------------------------------------------------------------------
315 * PCMCIA stuff
316 *-----------------------------------------------------------------------
317 */
318#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
319#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
320#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
321#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
322#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
323#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
324#define CFG_PCMCIA_IO_ADDR (0xEC000000)
325#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
326
327/*-----------------------------------------------------------------------
328 * PCMCIA Power Switch
329 *
330 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
331 * control the voltages on the PCMCIA slot which is connected to Port B
332 *-----------------------------------------------------------------------
333 */
334 /* Output pins */
335#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
336#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
337#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
338#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
339#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
340#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
341 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
342 TPS2205_SHDN)
343
344 /* Input pins */
345#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
346#define TPS2205_INPUTS ( TPS2205_OC )
347
348/*-----------------------------------------------------------------------
349 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
350 *-----------------------------------------------------------------------
351 */
352
353#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
354
355#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
356#undef CONFIG_IDE_LED /* LED for ide not supported */
357#undef CONFIG_IDE_RESET /* reset for ide not supported */
358
359#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
360#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
361
362#define CFG_ATA_IDE0_OFFSET 0x0000
363
364#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
365
366/* Offset for data I/O */
367#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
368
369/* Offset for normal register accesses */
370#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
371
372/* Offset for alternate registers */
373#define CFG_ATA_ALT_OFFSET 0x0100
374
375
376 /*-----------------------------------------------------------------------
377 *
378 *-----------------------------------------------------------------------
379 *
380 */
381#define CFG_DER 0
382
383/* Because of the way the 860 starts up and assigns CS0 the
384* entire address space, we have to set the memory controller
385* differently. Normally, you write the option register
386* first, and then enable the chip select by writing the
387* base register. For CS0, you must write the base register
388* first, followed by the option register.
389*/
390
391/*
392 * Init Memory Controller:
393 *
394 * BR0 and OR0 (FLASH)
395 */
396
397#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
398#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
399
400#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
401#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
402
403/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
404#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
405
406#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
407
408#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
409#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
410
411/*
412 * BR1 and OR1 (SDRAM)
413 */
414#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
415#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
416
417#define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
418
419#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
420#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
421
422/*
423 * Memory Periodic Timer Prescaler
424 */
425
426/* periodic timer for refresh */
427#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
428
429/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
430#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
431#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
432
433/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
434#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
435#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
436
437/*
438 * MAMR settings for SDRAM
439 */
440
441/* 8 column SDRAM */
442#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
445/* 9 column SDRAM */
446#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
449
450#define CFG_MAMR 0x13a01114
451/*
452 * Internal Definitions
453 *
454 * Boot Flags
455 */
456#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
457#define BOOTFLAG_WARM 0x02 /* Software reboot */
458
459#ifdef CONFIG_MPC860T
460
461/* Interrupt level assignments.
462*/
463#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
464
465#endif /* CONFIG_MPC860T */
466
467
468#endif /* __CONFIG_H */