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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2002
3 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
4 *
5 * This file is based on similar values for other boards found in other
6 * U-Boot config files, and some that I found in the EP8260 manual.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
wdenka562e1b2005-01-09 18:21:42 +000029 *
wdenk9dd611b2005-01-09 17:19:34 +000030 * "EP8260 H, V.1.1"
wdenk5b1d7132002-11-03 00:07:02 +000031 * - 64M 60x Bus SDRAM
32 * - 32M Local Bus SDRAM
33 * - 16M Flash (4 x AM29DL323DB90WDI)
34 * - 128k NVRAM with RTC
wdenk9dd611b2005-01-09 17:19:34 +000035 *
36 * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
37 * - 300MHz/133MHz/66MHz
38 * - 64M 60x Bus SDRAM
39 * - 32M Local Bus SDRAM
wdenka562e1b2005-01-09 18:21:42 +000040 * - 32M Flash
wdenk9dd611b2005-01-09 17:19:34 +000041 * - 128k NVRAM with RTC
wdenk5b1d7132002-11-03 00:07:02 +000042 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
wdenk9dd611b2005-01-09 17:19:34 +000047/* Define this to enable support the EP8260 H2 version */
48#define CFG_EP8260_H2 1
49/* #undef CFG_EP8260_H2 */
50
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050051#define CONFIG_CPM2 1 /* Has a CPM2 */
52
wdenk5b1d7132002-11-03 00:07:02 +000053/* What is the oscillator's (UX2) frequency in Hz? */
54#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
55
56/*-----------------------------------------------------------------------
57 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
58 *-----------------------------------------------------------------------
59 * What should MODCK_H be? It is dependent on the oscillator
60 * frequency, MODCK[1-3], and desired CPM and core frequencies.
61 * Here are some example values (all frequencies are in MHz):
62 *
63 * MODCK_H MODCK[1-3] Osc CPM Core
64 * ------- ---------- --- --- ----
65 * 0x2 0x2 33 133 133
66 * 0x2 0x3 33 133 166
67 * 0x2 0x4 33 133 200
68 * 0x2 0x5 33 133 233
69 * 0x2 0x6 33 133 266
70 *
71 * 0x5 0x5 66 133 133
72 * 0x5 0x6 66 133 166
73 * 0x5 0x7 66 133 200 *
74 * 0x6 0x0 66 133 233
75 * 0x6 0x1 66 133 266
76 * 0x6 0x2 66 133 300
77 */
wdenk9dd611b2005-01-09 17:19:34 +000078#ifdef CFG_EP8260_H2
79#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
80#else
81#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
82#endif
wdenk5b1d7132002-11-03 00:07:02 +000083
84/* Define this if you want to boot from 0x00000100. If you don't define
85 * this, you will need to program the bootloader to 0xfff00000, and
86 * get the hardware reset config words at 0xfe000000. The simplest
87 * way to do that is to program the bootloader at both addresses.
88 * It is suggested that you just let U-Boot live at 0x00000000.
89 */
90/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */
91/* #undef CFG_SBC_BOOT_LOW */
92
93/* The reset command will not work as expected if the reset address does
94 * not point to the correct address.
95 */
96
97#define CFG_RESET_ADDRESS 0xFFF00100
98
99/* What should the base address of the main FLASH be and how big is
100 * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
101 * The main FLASH is whichever is connected to *CS0. U-Boot expects
102 * this to be the SIMM.
103 */
wdenk9dd611b2005-01-09 17:19:34 +0000104#ifdef CFG_EP8260_H2
105#define CFG_FLASH0_BASE 0xFE000000
106#define CFG_FLASH0_SIZE 32
107#else
wdenk5b1d7132002-11-03 00:07:02 +0000108#define CFG_FLASH0_BASE 0xFF000000
wdenka562e1b2005-01-09 18:21:42 +0000109#define CFG_FLASH0_SIZE 16
wdenk9dd611b2005-01-09 17:19:34 +0000110#endif
wdenk5b1d7132002-11-03 00:07:02 +0000111
112/* What should the base address of the secondary FLASH be and how big
113 * is it (in Mbytes)? The secondary FLASH is whichever is connected
114 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
115 * want it enabled, don't define these constants.
116 */
117#define CFG_FLASH1_BASE 0
118#define CFG_FLASH1_SIZE 0
119#undef CFG_FLASH1_BASE
120#undef CFG_FLASH1_SIZE
121
122/* What should be the base address of SDRAM DIMM (60x bus) and how big is
123 * it (in Mbytes)?
124*/
125#define CFG_SDRAM0_BASE 0x00000000
126#define CFG_SDRAM0_SIZE 64
127
128/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
129 * local bus (8260 local bus is NOT cacheable!)
130*/
131/* #define CFG_LSDRAM */
wdenka562e1b2005-01-09 18:21:42 +0000132#undef CFG_LSDRAM
wdenk5b1d7132002-11-03 00:07:02 +0000133
134#ifdef CFG_LSDRAM
135/* What should be the base address of SDRAM DIMM (local bus) and how big is
136 * it (in Mbytes)?
137*/
138 #define CFG_SDRAM1_BASE 0x04000000
139 #define CFG_SDRAM1_SIZE 32
140#else
141 #define CFG_SDRAM1_BASE 0
142 #define CFG_SDRAM1_SIZE 0
143 #undef CFG_SDRAM1_BASE
144 #undef CFG_SDRAM1_SIZE
145#endif /* CFG_LSDRAM */
146
147/* What should be the base address of NVRAM and how big is
148 * it (in Bytes)
149 */
wdenk9dd611b2005-01-09 17:19:34 +0000150#define CFG_NVRAM_BASE_ADDR 0xFA080000
wdenk5b1d7132002-11-03 00:07:02 +0000151#define CFG_NVRAM_SIZE (128*1024)-16
152
153/* The RTC is a Dallas DS1556
154 */
155#define CONFIG_RTC_DS1556
156
157/* What should be the base address of the LEDs and switch S0?
158 * If you don't want them enabled, don't define this.
159 */
160#define CFG_LED_BASE 0x00000000
161#undef CFG_LED_BASE
162
163/*
164 * select serial console configuration
165 *
166 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
167 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
168 * for SCC).
169 *
170 * if CONFIG_CONS_NONE is defined, then the serial console routines must
171 * defined elsewhere.
172 */
173#define CONFIG_CONS_ON_SMC /* define if console on SMC */
174#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
175#undef CONFIG_CONS_NONE /* define if console on neither */
176#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
177
178/*
179 * select ethernet configuration
180 *
181 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
182 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
183 * for FCC)
184 *
185 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500186 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk5b1d7132002-11-03 00:07:02 +0000187 */
188#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
189#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
190#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
191#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
192
193#if ( CONFIG_ETHER_INDEX == 3 )
194
195/*
196 * - Rx-CLK is CLK15
197 * - Tx-CLK is CLK16
198 * - RAM for BD/Buffers is on the local Bus (see 28-13)
199 * - Enable Half Duplex in FSMR
200 */
201# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
202# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
203
204/*
205 * - RAM for BD/Buffers is on the local Bus (see 28-13)
206 */
207#ifdef CFG_LSDRAM
208 #define CFG_CPMFCR_RAMTYPE 3
209#else /* CFG_LSDRAM */
210 #define CFG_CPMFCR_RAMTYPE 0
211#endif /* CFG_LSDRAM */
212
213/* - Enable Half Duplex in FSMR */
214/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
215# define CFG_FCC_PSMR 0
216
217#else /* CONFIG_ETHER_INDEX */
218# error "on EP8260 ethernet must be FCC3"
219#endif /* CONFIG_ETHER_INDEX */
220
221/*
222 * select i2c support configuration
223 *
224 * Supported configurations are {none, software, hardware} drivers.
225 * If the software driver is chosen, there are some additional
226 * configuration items that the driver uses to drive the port pins.
227 */
228#undef CONFIG_HARD_I2C /* I2C with hardware support */
229#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
230#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
231#define CFG_I2C_SLAVE 0x7F
232
233/*
234 * Software (bit-bang) I2C driver configuration
235 */
236#ifdef CONFIG_SOFT_I2C
237#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
238#define I2C_ACTIVE (iop->pdir |= 0x00010000)
239#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
240#define I2C_READ ((iop->pdat & 0x00010000) != 0)
241#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
242 else iop->pdat &= ~0x00010000
243#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
244 else iop->pdat &= ~0x00020000
245#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
246#endif /* CONFIG_SOFT_I2C */
247
248/* #define CONFIG_RTC_DS174x */
249
250/* Define this to reserve an entire FLASH sector (256 KB) for
251 * environment variables. Otherwise, the environment will be
252 * put in the same sector as U-Boot, and changing variables
253 * will erase U-Boot temporarily
254 */
255#define CFG_ENV_IN_OWN_SECT
256
257/* Define to allow the user to overwrite serial and ethaddr */
258#define CONFIG_ENV_OVERWRITE
259
260/* What should the console's baud rate be? */
wdenk9dd611b2005-01-09 17:19:34 +0000261#ifdef CFG_EP8260_H2
262#define CONFIG_BAUDRATE 9600
263#else
wdenka562e1b2005-01-09 18:21:42 +0000264#define CONFIG_BAUDRATE 115200
wdenk9dd611b2005-01-09 17:19:34 +0000265#endif
wdenk5b1d7132002-11-03 00:07:02 +0000266
267/* Ethernet MAC address */
268#define CONFIG_ETHADDR 00:10:EC:00:30:8C
269
270#define CONFIG_IPADDR 192.168.254.130
271#define CONFIG_SERVERIP 192.168.254.49
272
273/* Set to a positive value to delay for running BOOTCOMMAND */
274#define CONFIG_BOOTDELAY -1
275
276/* undef this to save memory */
277#define CFG_LONGHELP
278
279/* Monitor Command Prompt */
280#define CFG_PROMPT "=> "
281
282/* Define this variable to enable the "hush" shell (from
283 Busybox) as command line interpreter, thus enabling
284 powerful command line syntax like
285 if...then...else...fi conditionals or `&&' and '||'
286 constructs ("shell scripts").
287 If undefined, you get the old, much simpler behaviour
288 with a somewhat smapper memory footprint.
289*/
290#define CFG_HUSH_PARSER
291#define CFG_PROMPT_HUSH_PS2 "> "
292
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500293
wdenk5b1d7132002-11-03 00:07:02 +0000294/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500295 * BOOTP options
296 */
297#define CONFIG_BOOTP_BOOTFILESIZE
298#define CONFIG_BOOTP_BOOTPATH
299#define CONFIG_BOOTP_GATEWAY
300#define CONFIG_BOOTP_HOSTNAME
301
302
303/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500304 * Command line configuration.
305 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200306#include <config_cmd_default.h>
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500307
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200308#define CONFIG_CMD_ASKENV
309#define CONFIG_CMD_BEDBUG
310#define CONFIG_CMD_CACHE
311#define CONFIG_CMD_CDP
312#define CONFIG_CMD_DATE
313#define CONFIG_CMD_DIAG
314#define CONFIG_CMD_ELF
315#define CONFIG_CMD_FAT
316#define CONFIG_CMD_I2C
317#define CONFIG_CMD_IMMAP
318#define CONFIG_CMD_IRQ
319#define CONFIG_CMD_PING
320#define CONFIG_CMD_PORTIO
321#define CONFIG_CMD_REGINFO
322#define CONFIG_CMD_SAVES
323#define CONFIG_CMD_SDRAM
324#define CONFIG_CMD_SNTP
325
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500326#undef CONFIG_CMD_DCR
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500327#undef CONFIG_CMD_XIMG
wdenk5b1d7132002-11-03 00:07:02 +0000328
329/* Where do the internal registers live? */
330#define CFG_IMMR 0xF0000000
331#define CFG_DEFAULT_IMMR 0x00010000
332
333/* Where do the on board registers (CS4) live? */
334#define CFG_REGS_BASE 0xFA000000
335
336/*****************************************************************************
337 *
338 * You should not have to modify any of the following settings
339 *
340 *****************************************************************************/
341
342#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
343#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
344
wdenkc837dcb2004-01-20 23:12:12 +0000345#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk5b1d7132002-11-03 00:07:02 +0000346
wdenk5b1d7132002-11-03 00:07:02 +0000347/*
348 * Miscellaneous configurable options
349 */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500350#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000351# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
352#else
353# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
354#endif
355
356/* Print Buffer Size */
357#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
358
359#define CFG_MAXARGS 8 /* max number of command args */
360
361#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
362
363#ifdef CFG_LSDRAM
364 #define CFG_MEMTEST_START 0x04000000 /* memtest works on */
365 #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
366#else
367 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
368 #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
369#endif /* CFG_LSDRAM */
370
371#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
372
373#define CFG_LOAD_ADDR 0x00100000 /* default load address */
374#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */
375
376#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
377
378/* valid baudrates */
379#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
380
381/*
382 * Low Level Configuration Settings
383 * (address mappings, register initial values, etc.)
384 * You should know what you are doing if you make changes here.
385 */
386
387#define CFG_FLASH_BASE CFG_FLASH0_BASE
388#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
389
390/*-----------------------------------------------------------------------
391 * Hard Reset Configuration Words
392 */
393
394#if defined(CFG_SBC_BOOT_LOW)
395# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
396#else
397# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
398#endif /* defined(CFG_SBC_BOOT_LOW) */
399
wdenk9dd611b2005-01-09 17:19:34 +0000400#ifdef CFG_EP8260_H2
401/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
402#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
403 ((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\
404 ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
wdenk5b1d7132002-11-03 00:07:02 +0000405
406#define CFG_HRCW_MASTER (HRCW_EBM |\
wdenk8bde7f72003-06-27 21:31:46 +0000407 HRCW_L2CPC01 |\
wdenk5b1d7132002-11-03 00:07:02 +0000408 CFG_SBC_HRCW_IMMR |\
409 HRCW_APPC10 |\
410 HRCW_CS10PC01 |\
wdenk9dd611b2005-01-09 17:19:34 +0000411 CFG_SBC_MODCK_H |\
wdenk5b1d7132002-11-03 00:07:02 +0000412 CFG_SBC_HRCW_BOOT_FLAGS)
wdenk9dd611b2005-01-09 17:19:34 +0000413#else
wdenk5b1d7132002-11-03 00:07:02 +0000414#define CFG_HRCW_MASTER 0x10400245
wdenk9dd611b2005-01-09 17:19:34 +0000415#endif
wdenk5b1d7132002-11-03 00:07:02 +0000416
417/* no slaves */
418#define CFG_HRCW_SLAVE1 0
419#define CFG_HRCW_SLAVE2 0
420#define CFG_HRCW_SLAVE3 0
421#define CFG_HRCW_SLAVE4 0
422#define CFG_HRCW_SLAVE5 0
423#define CFG_HRCW_SLAVE6 0
424#define CFG_HRCW_SLAVE7 0
425
426/*-----------------------------------------------------------------------
427 * Definitions for initial stack pointer and data area (in DPRAM)
428 */
429#define CFG_INIT_RAM_ADDR CFG_IMMR
430#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
431#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
432#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
433#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
434
435/*-----------------------------------------------------------------------
436 * Start addresses for the final memory configuration
437 * (Set up by the startup code)
438 * Please note that CFG_SDRAM_BASE _must_ start at 0
439 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
440 */
441#define CFG_MONITOR_BASE TEXT_BASE
442
443
444#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
445# define CFG_RAMBOOT
446#endif
447
448#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
449#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
450
451/*
452 * For booting Linux, the board info and command line data
453 * have to be in the first 8 MB of memory, since this is
454 * the maximum mapped by the Linux kernel during initialization.
455 */
456#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
457
458/*-----------------------------------------------------------------------
459 * FLASH and environment organization
460 */
461#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk9dd611b2005-01-09 17:19:34 +0000462#ifdef CFG_EP8260_H2
463#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
464#else
wdenk5b1d7132002-11-03 00:07:02 +0000465#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk9dd611b2005-01-09 17:19:34 +0000466#endif
wdenk5b1d7132002-11-03 00:07:02 +0000467
Wolfgang Denkbd516262005-09-25 16:56:15 +0200468#ifdef CFG_EP8260_H2
469#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
470#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
471#else
wdenk5b1d7132002-11-03 00:07:02 +0000472#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
473#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
Wolfgang Denkbd516262005-09-25 16:56:15 +0200474#endif
wdenk5b1d7132002-11-03 00:07:02 +0000475
476#ifndef CFG_RAMBOOT
477# define CFG_ENV_IS_IN_FLASH 1
478
479# ifdef CFG_ENV_IN_OWN_SECT
480# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
481# define CFG_ENV_SECT_SIZE 0x40000
482# else
483# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
484# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
485# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
486# endif /* CFG_ENV_IN_OWN_SECT */
487#else
488# define CFG_ENV_IS_IN_NVRAM 1
489# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
490# define CFG_ENV_SIZE 0x200
491#endif /* CFG_RAMBOOT */
492
493/*-----------------------------------------------------------------------
494 * Cache Configuration
495 */
496#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
497
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500498#if defined(CONFIG_CMD_KGDB)
wdenk5b1d7132002-11-03 00:07:02 +0000499# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
500#endif
501
502/*-----------------------------------------------------------------------
503 * HIDx - Hardware Implementation-dependent Registers 2-11
504 *-----------------------------------------------------------------------
505 * HID0 also contains cache control - initially enable both caches and
506 * invalidate contents, then the final state leaves only the instruction
507 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
508 * but Soft reset does not.
509 *
510 * HID1 has only read-only information - nothing to set.
511 */
512#define CFG_HID0_INIT (HID0_ICE |\
513 HID0_DCE |\
514 HID0_ICFI |\
515 HID0_DCI |\
516 HID0_IFEM |\
517 HID0_ABE)
518#ifdef CFG_LSDRAM
519/* 8260 local bus is NOT cacheable */
520#define CFG_HID0_FINAL (/*HID0_ICE |*/\
521 HID0_IFEM |\
522 HID0_ABE |\
523 HID0_EMCP)
524#else /* !CFG_LSDRAM */
525#define CFG_HID0_FINAL (HID0_ICE |\
526 HID0_IFEM |\
527 HID0_ABE |\
528 HID0_EMCP)
529#endif /* CFG_LSDRAM */
530
531#define CFG_HID2 0
532
533/*-----------------------------------------------------------------------
534 * RMR - Reset Mode Register
535 *-----------------------------------------------------------------------
536 */
537#define CFG_RMR 0
538
539/*-----------------------------------------------------------------------
540 * BCR - Bus Configuration 4-25
541 *-----------------------------------------------------------------------
542 */
wdenk9dd611b2005-01-09 17:19:34 +0000543#define CFG_BCR (BCR_EBM |\
wdenk5b1d7132002-11-03 00:07:02 +0000544 BCR_PLDP |\
545 BCR_EAV |\
wdenk9dd611b2005-01-09 17:19:34 +0000546 BCR_NPQM0)
547
wdenk5b1d7132002-11-03 00:07:02 +0000548/*-----------------------------------------------------------------------
549 * SIUMCR - SIU Module Configuration 4-31
550 *-----------------------------------------------------------------------
551 */
wdenk5b1d7132002-11-03 00:07:02 +0000552#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
wdenk8bde7f72003-06-27 21:31:46 +0000553 SIUMCR_APPC10 |\
554 SIUMCR_CS10PC01)
wdenk5b1d7132002-11-03 00:07:02 +0000555
wdenk5b1d7132002-11-03 00:07:02 +0000556/*-----------------------------------------------------------------------
557 * SYPCR - System Protection Control 11-9
558 * SYPCR can only be written once after reset!
559 *-----------------------------------------------------------------------
560 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
561 */
wdenk9dd611b2005-01-09 17:19:34 +0000562#ifdef CFG_EP8260_H2
wdenka562e1b2005-01-09 18:21:42 +0000563/* TBD: Find out why setting the BMT to 0xff causes the FCC to
564 * generate TX buffer underrun errors for large packets under
565 * Linux
wdenk9dd611b2005-01-09 17:19:34 +0000566 */
567#define CFG_SYPCR_BMT 0x00000600
568#else
569#define CFG_SYPCR_BMT SYPCR_BMT
570#endif
571
wdenk5b1d7132002-11-03 00:07:02 +0000572#ifdef CFG_LSDRAM
573#define CFG_SYPCR (SYPCR_SWTC |\
wdenk9dd611b2005-01-09 17:19:34 +0000574 CFG_SYPCR_BMT |\
wdenk8bde7f72003-06-27 21:31:46 +0000575 SYPCR_PBME |\
576 SYPCR_LBME |\
577 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000578#else
579#define CFG_SYPCR (SYPCR_SWTC |\
wdenk9dd611b2005-01-09 17:19:34 +0000580 CFG_SYPCR_BMT |\
wdenk8bde7f72003-06-27 21:31:46 +0000581 SYPCR_PBME |\
582 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000583#endif
wdenk9dd611b2005-01-09 17:19:34 +0000584
wdenk5b1d7132002-11-03 00:07:02 +0000585/*-----------------------------------------------------------------------
586 * TMCNTSC - Time Counter Status and Control 4-40
587 *-----------------------------------------------------------------------
588 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
589 * and enable Time Counter
590 */
591#define CFG_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000592 TMCNTSC_ALR |\
593 TMCNTSC_TCF |\
594 TMCNTSC_TCE)
wdenk5b1d7132002-11-03 00:07:02 +0000595
596/*-----------------------------------------------------------------------
597 * PISCR - Periodic Interrupt Status and Control 4-42
598 *-----------------------------------------------------------------------
599 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
600 * Periodic timer
601 */
wdenk9dd611b2005-01-09 17:19:34 +0000602#ifdef CFG_EP8260_H2
603#define CFG_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000604 PISCR_PTF |\
wdenk9dd611b2005-01-09 17:19:34 +0000605 PISCR_PTE)
606#else
wdenk5b1d7132002-11-03 00:07:02 +0000607#define CFG_PISCR 0
wdenk9dd611b2005-01-09 17:19:34 +0000608#endif
609
wdenk5b1d7132002-11-03 00:07:02 +0000610/*-----------------------------------------------------------------------
611 * SCCR - System Clock Control 9-8
612 *-----------------------------------------------------------------------
613 */
Wolfgang Denkbd516262005-09-25 16:56:15 +0200614#ifdef CFG_EP8260_H2
615#define CFG_SCCR (SCCR_DFBRG00)
616#else
wdenk5b1d7132002-11-03 00:07:02 +0000617#define CFG_SCCR (SCCR_DFBRG01)
Wolfgang Denkbd516262005-09-25 16:56:15 +0200618#endif
wdenk5b1d7132002-11-03 00:07:02 +0000619
620/*-----------------------------------------------------------------------
621 * RCCR - RISC Controller Configuration 13-7
622 *-----------------------------------------------------------------------
623 */
624#define CFG_RCCR 0
625
626/*-----------------------------------------------------------------------
627 * MPTPR - Memory Refresh Timer Prescale Register 10-32
628 *-----------------------------------------------------------------------
629 */
630#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK)
631
632/*
633 * Init Memory Controller:
634 *
635 * Bank Bus Machine PortSz Device
636 * ---- --- ------- ------ ------
637 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
638 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
639 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
640 * 3 unused
641 * 4 60x GPCM 8 bit Board Regs, NVRTC
642 * 5 unused
643 * 6 unused
644 * 7 unused
645 * 8 PCMCIA
646 * 9 unused
647 * 10 unused
648 * 11 unused
649*/
650
651/*-----------------------------------------------------------------------
652 * BRx - Base Register
653 * Ref: Section 10.3.1 on page 10-14
654 * ORx - Option Register
655 * Ref: Section 10.3.2 on page 10-18
656 *-----------------------------------------------------------------------
657 */
658
659/* Bank 0 - FLASH
660 *
661 */
662#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000663 BRx_PS_64 |\
wdenk5b1d7132002-11-03 00:07:02 +0000664 BRx_DECC_NONE |\
wdenk8bde7f72003-06-27 21:31:46 +0000665 BRx_MS_GPCM_P |\
666 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000667
668#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000669 ORxG_CSNT |\
670 ORxG_ACS_DIV1 |\
wdenk9dd611b2005-01-09 17:19:34 +0000671 ORxG_SCY_8_CLK |\
wdenk8bde7f72003-06-27 21:31:46 +0000672 ORxG_EHTR)
wdenk5b1d7132002-11-03 00:07:02 +0000673
674/* Bank 1 - SDRAM
675 * PSDRAM
676 */
677#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000678 BRx_PS_64 |\
679 BRx_MS_SDRAM_P |\
680 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000681
682#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000683 ORxS_BPD_4 |\
684 ORxS_ROWST_PBI1_A6 |\
685 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000686
wdenk9dd611b2005-01-09 17:19:34 +0000687#ifdef CFG_EP8260_H2
688#define CFG_PSDMR 0xC34E246E
689#else
wdenk5b1d7132002-11-03 00:07:02 +0000690#define CFG_PSDMR 0xC34E2462
wdenk9dd611b2005-01-09 17:19:34 +0000691#endif
wdenk5b1d7132002-11-03 00:07:02 +0000692
wdenk9dd611b2005-01-09 17:19:34 +0000693#define CFG_PSRT 0x64
wdenk5b1d7132002-11-03 00:07:02 +0000694
695#ifdef CFG_LSDRAM
696/* Bank 2 - SDRAM
697 * LSDRAM
698 */
699
700 #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000701 BRx_PS_32 |\
702 BRx_MS_SDRAM_L |\
703 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000704
705 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000706 ORxS_BPD_4 |\
707 ORxS_ROWST_PBI0_A9 |\
708 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000709
wdenk9dd611b2005-01-09 17:19:34 +0000710 #define CFG_LSDMR 0x416A2562
wdenk5b1d7132002-11-03 00:07:02 +0000711 #define CFG_LSRT 0x64
712#else
713 #define CFG_LSRT 0x0
714#endif /* CFG_LSDRAM */
715
716/* Bank 4 - On board registers
717 * NVRTC and BCSR
718 */
719#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000720 BRx_PS_8 |\
721 BRx_MS_GPCM_P |\
722 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000723/*
724#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000725 ORxG_CSNT |\
726 ORxG_ACS_DIV1 |\
727 ORxG_SCY_10_CLK |\
728 ORxG_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000729*/
730#define CFG_OR4_PRELIM 0xfff00854
731
wdenk9dd611b2005-01-09 17:19:34 +0000732#ifdef _NOT_USED_SINCE_NOT_WORKING_
wdenk5b1d7132002-11-03 00:07:02 +0000733/* Bank 8 - On board registers
734 * PCMCIA (currently not working!)
735 */
736#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000737 BRx_PS_16 |\
738 BRx_MS_GPCM_P |\
739 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000740
741#define CFG_OR8_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000742 ORxG_CSNT |\
743 ORxG_ACS_DIV1 |\
wdenk5b1d7132002-11-03 00:07:02 +0000744 ORxG_SETA |\
wdenk8bde7f72003-06-27 21:31:46 +0000745 ORxG_SCY_10_CLK)
wdenk9dd611b2005-01-09 17:19:34 +0000746#endif
wdenk5b1d7132002-11-03 00:07:02 +0000747
748/*
749 * Internal Definitions
750 *
751 * Boot Flags
752 */
753#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
754#define BOOTFLAG_WARM 0x02 /* Software reboot */
755
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200756/*
757 * JFFS2 partitions
758 *
759 */
760/* No command line, one static partition, whole device */
761#undef CONFIG_JFFS2_CMDLINE
762#define CONFIG_JFFS2_DEV "nor0"
763#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
764#define CONFIG_JFFS2_PART_OFFSET 0x00000000
765
766/* mtdparts command line support */
767/* Note: fake mtd_id used, no linux mtd map file */
768/*
769#define CONFIG_JFFS2_CMDLINE
770#define MTDIDS_DEFAULT ""
771#define MTDPARTS_DEFAULT ""
772*/
773
wdenk5b1d7132002-11-03 00:07:02 +0000774#endif /* __CONFIG_H */